Intel Embedded Intel486

3-3
INTERNAL ARCHITECTURE
Figure 3-2. Intel486™ SX Processor Block Diagram
Paging
Unit
Prefetcher
32-Byte Code
Queue

2x16 Bytes
Code
Stream
Barrel
Shifter
24
Cache Unit
Burst Bus
Control
Bus Control
Write Buffers
4 x 32
64-Bit Interunit Transfer Bus
Register
File
ALU
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
32
Base/
Index
Bus
Translation
Lookaside
Buffer
20
8 Kbyte
Cache
Control &
Protection
Test Unit
Control
ROM
Address
Drivers
32
32
Data Bus
Transceivers
32
Request
Sequencer
Bus Size
Control
Cache
Control
Parity
Generation
and Control
Boundary
Scan
Control
Bus Interface
D31-D0
A31-A2
BE3#- BE0#
ADS# W/R# D/C# M/IO#
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
FERR# IGNNE#
STPCLK#
A5443-01
BRDY# BLAST#
BS16# BS8#
KEN# FLUSH#
AHOLD EADS#
DP3-DP0 PCHK#
TCK TMS
TDI TD0
128
Instruction
Decode
32
Decoded
Instruction
Path
PCD
PWT
2
Physical
Address
32-Bit Data Bus
32-Bit Data Bus
Linear Address
Micro-
Instruction
Displacement Bus
32