DAC Sample Rate:
The DAC Sample rate is always in the range of 53.76 GSa/s … 65 GSa/s. The DAC
sample rate indicates how many samples per seconds the DAC can generate. The
unit of the sample rate is Sa/s
DAC Sample Frequency:
The DAC Sample frequency is always in the range of 53.76 GHz … 65 GHz. As the
DAC sample frequency references to a clock, the unit of the sample frequency is Hz.
DAC Sample CLK:
The DAC Sample CLK is the clock signal that sources the four DAC of the M8195A.
There is a variable delay element between the clock generation block and the DAC.
SyncClock:
SyncClock = DAC Sample Rate / 256
The SyncClock is the timing reference for the M8195A. Latency specifications such as
the trigger to output latency are referenced to it. Also, the set-up and hold timing
specification for synchronous trigger is referenced to the Sync Clock. The sequencer
is also working with this clock. The Sync Clock is an internal clock signal that can be
output at the Reference Clock Out in order to accurately align the timing with an
external DUT or additional test equipment.
Delay Alignment:
The Synch Clock is the internal timing reference of the M8195A. After power on and
after each DAC sample rate change, the M8195A performs an internal delay
alignment. This delay alignment ensures that the latency from a synchronously
applied Trigger or Event signal is 157 Synch Clock cycles.
Synchronous operation:
Synchronous operation means that the M8195A is started synchronously with an
externally applied trigger. Also, sequencing is controlled synchronously by externally
applied Trigger or Event signals. In order to operate the M8195A synchronously, the
SynchClock must be output at the Reference Clock Out, which can be done by
setting internal switches accordingly. The Trigger and Event signal must meet set-up
and hold timing requirements as specified in the data sheet of the M8195A. The
latency (Trigger In to DATA_OUT or Event In to DATA_OUT) through the M8195A has
no variation.
Asynchronous operation:
Asynchronous operation means that the M8195A is started asynchronously with an
externally applied trigger. Also, sequencing is controlled asynchronously by
externally applied Trigger or Event signals. For asynchronous operation, it is not
required to output the SynchClock at the Reference Clock Out and consistently there
are no set-up and hold timing requirements to be met. The latency (Trigger In to
DATA_OUT or Event In to DATA_OUT) through the M8195A has a small uncertainty.
Please refer to the data sheet for the Delay accuracy specification
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