The variable delay is used in order to compensate for e.g. external cable length
differences as well as the initial skew. The variable delay has a very high timing
resolution. Modifying the variable delay always affects the delay of all four Data
Outputs.
Setting the variable delay to e.g. 10 ps has following effects:
Data Out 1, Data Out 2, Data Out 3, and Data Out 4 are delayed by 10 ps with
respect to Trigger/Gate Input or Event Input.
Data Out 1, Data Out 2, DataOut 3, and Data Out 4 are delayed by 10 ps with respect
to the internal Sync Clock. Note that the Sync Clock is the M8195A timing reference
that can be output at Ref Clk out.
In case the M8195A is sourced from Ref CLk In (or the AXIe backplane), Data Out1,
Data Out 2, Data Out 3, and Data Out 4 are delayed by 10 ps with respect to Ref CLk
In (or the AXIe backplane).
In case the M8197A synchronization module is used to configure a synchronous
system of multiple M8195A AWGs, the variable delay can be used to align the Data
Out among individual M8195A AWGs.
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