Keysight M8195A - Timing Block Diagram

1 Introduction
28 Keysight M8195A Revision 2 – Arbitrary Waveform Generator User’s Guide
1.5.2 Timing Block Diagram
The drawing below shows a block diagram of the instrument.
Extended Waveform
Memory
(16 GSa)
FPGA
Trigger In
DAC 1
DAC 2
FIR
FIR
FIR
FIR
Internal
Waveform
Memory
4 * 65 GSa/s
1 * 65 GSa/s or
2 * 32.5 GSa/s or
4 * 16.25 GSa/s
4 Differential Outputs
DAC 3
DAC 4
Event In
SyncClock
Reference Clock In
AXIe Backplane
Internal
Reference
Clock Generation
Reference Clock Out
Variable
Delay
DAC Sample Clk
:256
SyncClock
Asynch
path
Asynch
path
Figure 5: M8195A Timing Block Diagram
The level of detail is chosen to provide a general high level understanding of how the
instrument is working. Therefore, not all of ports are shown in the above diagram.