Motorola MC68020 - Page 102

5- 54 M68020 USER’S MANUAL MOTOROLA
The acceptable bus cycle terminations for asynchronous cycles are summarized in
relation to DSACK1/DSACK0 assertion as follows (case numbers refer to Table 5-8):
Normal Termination:
DSACK1/DSACK0 is asserted; BERR and HALT remain negated (case 1).
Halt Termination:
HALT is asserted at same time or before DSACK1/DSACK0, and BERR remains
negated (case 2).
Bus Error Termination:
BERR is asserted in lieu of, at the same time, or before DSACK1/DSACK0 (case 3) or
after DSACK1/DSACK0 (case 4), and HALT remains negated; BERR is negated at the
same time or after DSACK1/DSACK0.
Retry Termination:
HALT and BERR are asserted in lieu of, at the same time, or before DSACK1/DSACK0
(case 5) or after DSACK1/DSACK0 (case 6); BERR is negated at the same time or after
DSACK1/DSACK0; HALT may be negated at the same time or after BERR.
Table 5-8.
DSACK1/DSACK0
,
BERR
,
HALT
Assertion Results
Asserted on Rising
Edge of State
Case No. Control Signal n n+2 Result
1 DSACK1/DSACK0
BERR
HALT
A
N
N
S
N
X
Normal cycle terminate and continue.
2 DSACK1/DSACK0
BERR
HALT
A
N
A/S
S
N
S
Normal cycle terminate and halt. Continue when
HALT negated.
3 DSACK1/DSACK0
BERR
HALT
N/A
A
N
X
S
N
Terminate and take bus error exception, possibly
deferred.
4 DSACK1/DSACK0
BERR
HALT
A
N
N
X
A
N
Terminate and take bus error exception, possibly
deferred.
5 DSACK1/DSACK0
BERR
HALT
N/A
A
A/S
X
S
S
Terminate and retry when HALT negated.
6 DSACK1/DSACK0
BERR
HALT
A
N
N
X
A
A
Terminate and retry when HALT negated.
Legend:
n—The number of current even bus state (e.g., S2, S4, etc.)
A—Signal is asserted in this bus state
N—Signal is not asserted and/or remains negated in this bus state
X—Don’t care
S—Signal was asserted in previous state and remains asserted in this state