Interface Configuration Guide 7705 SAR Interfaces
Edition: 01 3HE 11011 AAAC TQZZA 467
The following can be configured for adaptive timing:
• 16-port T1/E1 ASAP Adapter card
• 32-port T1/E1 ASAP Adapter card
• T1/E1 ports on the 7705 SAR-M (variants with T1/E1 ports) on T1/E1 CES circuits used
for TDM pseudowires
• T1/E1 ports on the 7705 SAR-X on T1/E1 CES circuits used for TDM pseudowires
• T1/E1 ports on the 7705 SAR-A (variant with T1/E1 ports) on T1/E1 CES circuits used
for TDM pseudowires
• T1/E1 ports on the 4-port T1/E1 and RS-232 Combination module
The following can be configured for differential timing:
• 16-port T1/E1 ASAP Adapter card, version 2
• 32-port T1/E1 ASAP Adapter card
• T1/E1 channels on the 4-port OC3/STM1 / 1-port OC12/STM4 Adapter card
• T1/E1 channels on the DS3 ports on the 4-port DS3/E3 Adapter card (E3 ports cannot
be channelized)
• T1/E1 ports on the 7705 SAR-M (variants with T1/E1 ports)
• T1/E1 ports on the 7705 SAR-X
• T1/E1 ports on the 7705 SAR-A (variants with T1/E1 ports)
• T1/E1 ports on the 4-port T1/E1 and RS-232 Combination module
The clock source setting also determines the node sync reference if the port is configured as
one of the node sync references (config>system>sync-if-timing>{ref1 | ref2}> source-
port command). Refer to the 7705 SAR Basic System Configuration Guide, “Node Timing”,
for more information.
Default node-timed
Parameters loop-timed — the link recovers the clock from the received data stream
node-timed — the link uses the internal clock when transmitting data
adaptive — clocking is derived from the incoming pseudowire packets from the MPLS
network
differential — clocking is derived from a common clock compared to differential clock
recovery (DCR) data in the RTP header in the TDM PW overhead. DCR must also
be enabled on the relevant card, module, or chassis with the clock-mode command.
Note: If a timing reference from an external BITS clock is used on a dedicated T1/E1 port,
the port must be configured as loop-timed.
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