RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 173
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (22/32)
Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range After
reset
1-bit 8-bit 16-bit
F047EH CAN receive buffer register 13DH
Note 2
RMDF313L RMDF313 R – √ √ 0000H
F047FH RMDF313H – √
F0480H CAN receive buffer register 14AL
Note 2
RMIDL14L RMIDL14 R – √ √ 0000H
F0481H RMIDL14H – √
F0482H CAN receive buffer register 14AH
Note 2
RMIDH14L RMIDH14 R – √ √ 0000H
F0483H RMIDH14H – √
F0484H CAN receive buffer register 14BL
Note 2
RMTS14L RMTS14 R – √ √ 0000H
F0485H RMTS14H – √
F0486H CAN receive buffer register 14BH
Note 2
RMPTR14L RMPTR14 R – √ √ 0000H
F0487H RMPTR14H – √
F0488H CAN receive buffer register 14CL
Note 2
RMDF014L RMDF014 R – √ √ 0000H
F0489H RMDF014H – √
F048AH CAN receive buffer register 14CH
Note 2
RMDF114L RMDF114 R – √ √ 0000H
F048BH RMDF114H – √
F048CH CAN receive buffer register 14DL
Note 2
RMDF214L RMDF214 R – √ √ 0000H
F048DH RMDF214H – √
F048EH CAN receive buffer register 14DH
Note 2
RMDF314L RMDF314 R – √ √ 0000H
F048FH RMDF314H – √
F0490H CAN receive buffer register 15AL
Note 2
RMIDL15L RMIDL15 R – √ √ 0000H
F0491H RMIDL15H – √
F0492H CAN receive buffer register 15AH
Note 2
RMIDH15L RMIDH15 R – √ √ 0000H
F0493H RMIDH15H – √
F0494H CAN receive buffer register 15BL
Note 2
RMTS15L RMTS15 R – √ √ 0000H
F0495H RMTS15H – √
F0496H CAN receive buffer register 15BH
Note 2
RMPTR15L RMPTR15 R – √ √ 0000H
F0497H RMPTR15H – √
F0498H CAN receive buffer register 15CL
Note 2
RMDF015L RMDF015 R – √ √ 0000H
F0499H RMDF015H – √
F049AH CAN receive buffer register 15CH
Note 2
RMDF115L RMDF115 R – √ √ 0000H
F049BH RMDF115H – √
F049CH CAN receive buffer register 15DL
Note 2
RMDF215L RMDF215 R – √ √ 0000H
F049DH RMDF215H – √
F049EH CAN receive buffer register 15DH
Note 2
RMDF315L RMDF315 R – √ √ 0000H
F049FH RMDF315H – √
F0580H CAN RAM test register 0
Note 1
RPGACC0L RPGACC0 R/W – √ √ 0000H
F0581H RPGACC0H – √
F0582H CAN RAM test register 1
Note 1
RPGACC1L RPGACC1 R/W – √ √ 0000H
F0583H RPGACC1H – √
F0584H CAN RAM test register 2
Note 1
RPGACC2L RPGACC2 R/W – √ √ 0000H
F0585H RPGACC2H – √
F0586H CAN RAM test register 3
Note 1
RPGACC3L RPGACC3 R/W – √ √ 0000H
F0587H RPGACC3H – √
F0588H CAN RAM test register 4
Note 1
RPGACC4L RPGACC4 R/W – √ √ 0000H
F0589H RPGACC4H – √
F058AH CAN RAM test register 5
Note 1
RPGACC5L RPGACC5 R/W – √ √ 0000H
F058BH RPGACC5H – √
Notes 1. These registers are allocated to the RAM window 0 for the CAN module (receive rule and CAN RAM test register).
When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to the RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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