RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 174
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (23/32)
Address Special Function Register (2nd SFR)
Name
Symbol R/W Manipulable Bit Range After
reset
1-bit 8-bit 16-bit
F058CH CAN RAM test register 6
Note 1
RPGACC6L RPGACC6 R/W – √ √ 0000H
F058DH RPGACC6H – √
F058EH CAN RAM test register 7
Note 1
RPGACC7L RPGACC7 R/W – √ √ 0000H
F058FH RPGACC7H – √
F0590H CAN RAM test register 8
Note 1
RPGACC8L RPGACC8 R/W – √ √ 0000H
F0591H RPGACC8H – √
F0592H CAN RAM test register 9
Note 1
RPGACC9L RPGACC9 R/W – √ √ 0000H
F0593H RPGACC9H – √
F0594H CAN RAM test register 10
Note 1
RPGACC10L RPGACC10 R/W – √ √ 0000H
F0595H RPGACC10H – √
F0596H CAN RAM test register 11
Note 1
RPGACC11L RPGACC11 R/W – √ √ 0000H
F0597H RPGACC11H – √
F0598H CAN RAM test register 12
Note 1
RPGACC12L RPGACC12 R/W – √ √ 0000H
F0599H RPGACC12H – √
F059AH CAN RAM test register 13
Note 1
RPGACC13L RPGACC13 R/W – √ √ 0000H
F059BH RPGACC13H – √
F059CH CAN RAM test register 14
Note 1
RPGACC14L RPGACC14 R/W – √ √ 0000H
F059DH RPGACC14H – √
F059EH CAN RAM test register 15
Note 1
RPGACC15L RPGACC15 R/W – √ √ 0000H
F059FH RPGACC15H – √
F05A0H CAN RAM test register 16
Note 1
RPGACC16L RPGACC16 R/W – √ √ 0000H
F05A1H RPGACC16H – √
F05A0H CAN receive FIFO access register 0AL
Note 2
RFIDL0L RFIDL0 R – √ √ 0000H
F05A1H RFIDL0H – √
F05A2H CAN RAM test register 17
Note 1
RPGACC17L RPGACC17 R/W – √ √ 0000H
F05A3H RPGACC17H – √
F05A2H CAN receive FIFO access register 0AH
Note 2
RFIDH0L RFIDH0 R – √ √ 0000H
F05A3H RFIDH0H – √
F05A4H CAN RAM test register 18
Note 1
RPGACC18L RPGACC18 R/W – √ √ 0000H
F05A5H RPGACC18H – √
F05A4H CAN receive FIFO access register 0BL
Note 2
RFTS0L RFTS0 R – √ √ 0000H
F05A5H RFTS0H – √
F05A6H CAN RAM test register 19
Note 1
RPGACC19L RPGACC19 R/W – √ √ 0000H
F05A7H RPGACC19H – √
F05A6H CAN receive FIFO access register 0BH
Note 2
RFPTR0L RFPTR0 R – √ √ 0000H
F05A7H RFPTR0H – √
F05A8H CAN RAM test register 20
Note 1
RPGACC20L RPGACC20 R/W – √ √ 0000H
F05A9H RPGACC20H – √
F05A8H CAN receive FIFO access register 0CL
Note 2
RFDF00L RFDF00 R – √ √ 0000H
F05A9H RFDF00H – √
F05AAH CAN RAM test register 21
Note 1
RPGACC21L RPGACC21 R/W – √ √ 0000H
F05ABH RPGACC21H – √
F05AAH CAN receive FIFO access register 0CH
Note 2
RFDF10L RFDF10 R – √ √ 0000H
F05ABH RFDF10H – √
F05ACH CAN RAM test register 22
Note 1
RPGACC22L RPGACC22 R/W – √ √ 0000H
F05ADH RPGACC22H – √
Notes 1. These registers are allocated to the RAM window 0 for the CAN module (receive rule and CAN RAM test register).
When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to the RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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