RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 175
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (24/32)
Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range After
reset
1-bit 8-bit 16-bit
F05ACH CAN receive FIFO access register 0DL
Note 2
RFDF20L RFDF20 R – √ √ 0000H
F05ADH RFDF20H – √
F05AEH CAN RAM test register 23
Note 1
RPGACC23L RPGACC23 R/W – √ √ 0000H
F05AFH RPGACC23H – √
F05AEH CAN receive FIFO access register 0DH
Note 2
RFDF30L RFDF30 R – √ √ 0000H
F05AFH RFDF30H – √
F05B0H CAN RAM test register 24
Note 1
RPGACC24L RPGACC24 R/W – √ √ 0000H
F05B1H RPGACC24H – √
F05B0H CAN receive FIFO access register 1AL
Note 2
RFIDL1L RFIDL1 R – √ √ 0000H
F05B1H RFIDL1H – √
F05B2H CAN RAM test register 25
Note 1
RPGACC25L RPGACC25 R/W – √ √ 0000H
F05B3H RPGACC25H – √
F05B2H CAN receive FIFO access register 1AH
Note 2
RFIDH1L RFIDH1 R – √ √ 0000H
F05B3H RFIDH1H – √
F05B4H CAN RAM test register 26
Note 1
RPGACC26L RPGACC26 R/W – √ √ 0000H
F05B5H RPGACC26H – √
F05B4H CAN receive FIFO access register 1BL
Note 2
RFTS1L RFTS1 R – √ √ 0000H
F05B5H RFTS1H – √
F05B6H CAN RAM test register 27
Note 1
RPGACC27L RPGACC27 R/W – √ √ 0000H
F05B7H RPGACC27H – √
F05B6H CAN receive FIFO access register 1BH
Note 2
RFPTR1L RFPTR1 R – √ √ 0000H
F05B7H RFPTR1H – √
F05B8H CAN RAM test register 28
Note 1
RPGACC28L RPGACC28 R/W – √ √ 0000H
F05B9H RPGACC28H – √
F05B8H CAN receive FIFO access register 1CL
Note 2
RFDF01L RFDF01 R – √ √ 0000H
F05B9H RFDF01H – √
F05BAH CAN RAM test register 29
Note 1
RPGACC29L RPGACC29 R/W – √ √ 0000H
F05BBH RPGACC29H – √
F05BAH CAN receive FIFO access register 1CH
Note 2
RFDF11L RFDF11 R – √ √ 0000H
F05BBH RFDF11H – √
F05BCH CAN RAM test register 30
Note 1
RPGACC30L RPGACC30 R/W – √ √ 0000H
F05BDH RPGACC30H – √
F05BCH CAN receive FIFO access register 1DL
Note 2
RFDF21L RFDF21 R – √ √ 0000H
F05BDH RFDF21H – √
F05BEH CAN RAM test register 31
Note 1
RPGACC31L RPGACC31 R/W – √ √ 0000H
F05BFH RPGACC31H – √
F05BEH CAN receive FIFO access register 1DH
Note 2
RFDF31L RFDF31 R – √ √ 0000H
F05BFH RFDF31H – √
F05C0H CAN RAM test register 32
Note 1
RPGACC32L RPGACC32 R/W – √ √ 0000H
F05C1H RPGACC32H – √
F05C2H CAN RAM test register 33
Note 1
RPGACC33L RPGACC33 R/W – √ √ 0000H
F05C3H RPGACC33H – √
F05C4H CAN RAM test register 34
Note 1
RPGACC34L RPGACC34 R/W – √ √ 0000H
F05C5H RPGACC34H – √
F05C6H CAN RAM test register 35
Note 1
RPGACC35L RPGACC35 R/W – √ √ 0000H
F05C7H RPGACC35H – √
Notes 1. These registers are allocated to the RAM window 0 for the CAN module (receive rule and CAN RAM test register).
When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to the RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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