RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 373
Dec 10, 2015
Cautions 1. Be sure to set bits 0 to 3 of the CKC register to 0.
2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the
CPU clock is changed, therefore, the clock supplied to peripheral hardware (except
the real-time clock, clock output/buzzer output, and watchdog timer) is also changed
at the same time. Consequently, stop each peripheral function when changing the
CPU/peripheral hardware clock.
3. If the subsystem clock or low-speed on-chip oscillator clock is used as the
peripheral hardware clock, the operations of the A/D converter and IICA are not
guaranteed. For the operating characteristics of the peripheral hardware, refer to the
chapters describing the various peripheral hardware as well as CHAPTER 34 to
CHAPTER 36 ELECTRICAL SPECIFICATIONS.
4. When selecting f
IH as the count source for timer RD, set fCLK to fMP before setting bit 4
(TRD0EN) in peripheral enable register 1 (PER1). When changing f
CLK to a clock other
than fMP, clear bit 4 (TRD0EN) in peripheral enable register 1 (PER1) before changing.
Remark For setting of the PLL clock, refer to 5.6.4 Examples of Setting PLL Circuit.
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