Date Code 20001006 Trip and Target Logic 5-5
SEL-351 Instruction Manual
The front-panel TARGET RESET button or the TAR R (Target Reset) serial port command are
primarily used during testing. Use these to force the TRIP Relay Word bit to logical 0 if test
conditions are such that setting ULTR does not assert to logical 1 to automatically deassert the
TRIP Relay Word bit instead.
Other Applications for the Target Reset Function
Refer to the bottom of Figure 5.1. Note that the combination of the TARGET RESET Pushbutton
and the TAR R (Target Reset) serial port command is also available as Relay Word bit TRGTR.
See Figure 5.17 and accompanying text for applications for Relay Word bit TRGTR.
Factory Settings Example (Using Setting TR)
If the “communications-assisted” and “switch-onto-fault” trip logic at the top of Figure 5.1 can
effectively be ignored, the figure becomes a lot smaller. Then SELOGIC Control Equation trip
setting TR is the only input into OR-1 gate and follows into the “seal-in and unlatch” logic for
Relay Word bit TRIP.
The factory settings for the trip logic SELOGIC Control Equation settings are:
TR = OC + 51PT + 51GT + 81D1T + LB3 + 50P1 * SH0 (trip conditions)
ULTR = !(51P + 51G) (unlatch trip conditions)
The factory setting for the Minimum Trip Duration Timer setting is:
TDURD = 9.000 cycles
See the settings sheets in Section 9: Setting the Relay for setting ranges.
Set Trip
In SELOGIC Control Equation setting TR = OC + 51PT + 51GT + 81D1T + LB3 + 50P1 * SH0:
• Time-overcurrent elements 51PT and 51GT trip directly. Time-overcurrent and definite-
time overcurrent elements can be torque controlled (e.g., elements 51PT and 51GT are
torque controlled by SELOGIC Control Equation settings 51PTC and 51GTC,
respectively). Check torque control settings to see if any control is applied to time-
overcurrent and definite-time overcurrent elements. Such control is not apparent by mere
inspection of trip setting TR or any other SELOGIC Control Equation trip setting.
• Frequency element 81D1T trips directly.
• Local bit LB3 trips directly (operates as a manual trip switch via the front panel). See
Local Control Switches in Section 7: Inputs, Outputs, Timers, and Other Control
Logic for more information on local bits.
• Phase instantaneous overcurrent element 50P1 is supervised by Relay Word bit SH0 in an
ANDed condition 50P1 * SH0. Elements 50P1 can only generate a trip when
SH0 = logical 1 (reclosing relay is at shot = 0). After the first trip in a reclose cycle, the
shot counter increments from 0 to 1, SH0 = logical 0, and element 50P1 cannot generate a
trip. See Section 6: Close and Reclose Logic for more information on reclosing relay
operation.
Courtesy of NationalSwitchgear.com
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