7-18 Inputs, Outputs, Timers, and Other Control Logic Date Code 20001006
SEL-351 Instruction Manual
Latch Control Switch States Retained
Power Loss
The states of the latch bits (LT1 through LT8) are retained if power to the relay is lost and then
restored. If a latch bit is asserted (e.g., LT2 = logical 1) when power is lost, it comes back
asserted (LT2 = logical 1) when power is restored. If a latch bit is deasserted (e.g., LT3 =
logical 0) when power is lost, it comes back deasserted (LT3 = logical 0) when power is restored.
This feature makes the latch bit feature behave the same as traditional latching relays. In a
traditional installation, if power is lost to the panel, the latching relay output contact position
remains unchanged.
Note: If a latch bit is set to a programmable output contact (e.g., OUT3 = LT2) and power to the
relay is lost, the state of the latch bit is stored in nonvolatile memory but the output contact
will go to its deenergized state. When power to the relay is restored, the programmable
output contact will go back to the state of the latch bit.
Settings Change or Active Setting Group Change
If individual settings are changed (for the active setting group or one of the other setting groups) or
the active setting group is changed, the states of the latch bits (Relay Word bits LT1 through LT8)
are retained, much like in the preceding “Power Loss” explanation.
If individual settings are changed for a setting group other than the active setting group, there is no
interruption of the latch bits (the relay is not momentarily disabled).
If the individual settings change or active setting group change causes a change in SELOGIC
Control Equation settings SETn or RSTn (n = 1 through 8), the retained states of the latch bits can
be changed, subject to the newly enabled settings SETn or RSTn.
Reset Latch Bits for Active Setting Group Change
If desired, the latch bits can be reset to logical 0 right after a settings group change, using
SELOGIC Control Equation setting RSTn (n = 1 through 8). Relay Word bits SG1 through SG6
indicate the active setting Group 1 through 6, respectively (see Table 7.3).
For example, when setting Group 4 becomes the active setting group, latch bit LT2 should be reset.
Make the following SELOGIC Control Equation settings in setting Group 4:
SV7 = SG4
RST2 = !SV7T + ... [= NOT(SV7T) + ...]
Courtesy of NationalSwitchgear.com