7-16 Inputs, Outputs, Timers, and Other Control Logic Date Code 20001006
SEL-351 Instruction Manual
For example in Figure 7.15, if:
LT1 = logical 0
input IN4 is routed to setting SET1 (as discussed previously):
SET1 = /IN4 = rising edge of input IN4
If input IN4 is then asserted for a few cycles by the SCADA contact (see Pulse 1 in Figure 7.16),
SET1 is asserted to logical 1 for one processing interval. This causes latch bit LT1 to change state
to:
LT1 = logical 1
the next processing interval.
With latch bit LT1 now at logical 1 for the next processing interval, input IN4 is routed to setting
RST1 (as discussed previously):
RST1 = /IN4 = rising edge of input IN4
This would then appear to enable the “reset” input (setting RST1) the next processing interval.
But the “rising edge” condition occurred the preceding processing interval. /IN4 is now at
logical 0, so setting RST1 does not assert, even though input IN4 remains asserted for at least a
few cycles by the SCADA contact.
If the SCADA contact deasserts and then asserts again (new rising edge – see Pulse 2 in
Figure 7.16), the “reset” input (setting RST1) asserts and latch bit LT1 deasserts back to logical 0
again. Thus each individual assertion of input IN4 (Pulse 1, Pulse 2, Pulse 3, and Pulse 4 in
Figure 7.16) changes the state of latch control switch just once.
Note: Refer to preceding subsection Optoisolated Inputs and Figure 7.1. Relay Word bit IN4
shows the state of optoisolated input IN4 after the input pickup/dropout debounce timer
IN4D. Thus, when using Relay Word bit IN4 in Figure 7.13 and Figure 7.14 and
associated SELOGIC Control Equations, keep in mind any time delay produced by the
input pickup/dropout debounce timer IN4D.
Courtesy of NationalSwitchgear.com
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