Schweitzer Engineering Laboratories SEL-352-1 - Page 72

iv Breaker Logic Date Code 20010731
SEL-352-1, -2 Instruction Manual
FIGURES
Figure 3.1: Basic Breaker Failure Protection Scheme............................................................................ 3-2
Figure 3.2: Basic Breaker Failure Scheme Timing ................................................................................ 3-2
Figure 3.3: Breaker Failure in a Complex Bus/Breaker Arrangement ................................................... 3-3
Figure 3.4: Single-Phase Diagram of AC Inputs to the Relay................................................................ 3-4
Figure 3.5: Subsidence Current Logic .................................................................................................... 3-6
Figure 3.6: A-Phase Failure to Trip for Fault Logic, Scheme 1 ............................................................. 3-8
Figure 3.7: Scheme 1 Breaker Failure Timing ....................................................................................... 3-9
Figure 3.8: A-Phase Failure to Trip for Fault Logic, Scheme 2 ........................................................... 3-10
Figure 3.9: Scheme 2 Breaker Failure Timing .....................................................................................3-11
Figure 3.10: A-Phase Failure to Trip for Fault Logic, Scheme 3........................................................... 3-11
Figure 3.11: Scheme 3 Breaker Failure Timing ..................................................................................... 3-12
Figure 3.12: A-Phase Failure to Trip for Fault Logic, Scheme 4........................................................... 3-12
Figure 3.13: Scheme 4 Breaker Failure Timing ..................................................................................... 3-13
Figure 3.14: A-Phase Failure to Trip for Fault Logic, Scheme 5........................................................... 3-14
Figure 3.15: Scheme 5 Breaker Failure Timing ..................................................................................... 3-14
Figure 3.16: RMS Overcurrent Condition Detection ............................................................................. 3-16
Figure 3.17: A-Phase Failure to Trip Load or Line-Charging Current Logic, Scheme 1 ...................... 3-19
Figure 3.18: Failure to Trip Load or Line-Charging Current Logic, Scheme 2 ..................................... 3-20
Figure 3.19: Trip and Close Resistor Thermal Protection Logic ........................................................... 3-24
Figure 3.20: A-Phase Voltage Nulling Logic ......................................................................................... 3-25
Figure 3.21: Flashover Condition Logic, Scheme 1–Six PTs ................................................................ 3-34
Figure 3.22: Flashover Condition Logic, Scheme 2–Three PTs ............................................................ 3-34
Figure 3.23: Current Unbalance, Failure to Close Logic........................................................................ 3-39
Figure 3.24: Single-Line Diagram for Open Conductor Condition........................................................ 3-42
Figure 3.25: Loss-of-Dielectric Detection Timing................................................................................. 3-43
Figure 3.26: Loss-of-Dielectric Detection Logic ................................................................................... 3-44
Figure 3.27: Breaker Alarm (BALRM) Logic........................................................................................3-46
Figure 3.28: Failed CB Trip Resistors Put in Service ............................................................................3-46
Figure 3.29: Failed CB Close Resistors Put in Service .......................................................................... 3-47
Figure 3.30: 52A Contradicts Voltage.................................................................................................... 3-47
Figure 3.31: Current While Open ........................................................................................................... 3-48
Figure 3.32: Trip While Open................................................................................................................. 3-48
Figure 3.33: Breaker Did Not Close ....................................................................................................... 3-48
Figure 3.34: Current After MOD Trip.................................................................................................... 3-49
Figure 3.35: MOD Contradicts Current.................................................................................................. 3-49
Figure 3.36: Slow Trip............................................................................................................................ 3-49
Figure 3.37: Slow Close.......................................................................................................................... 3-50
Figure 3.38: Potential Transformers Disagree........................................................................................ 3-50