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List of Figures
1-1. CC253x Block Diagram................................................................................................... 20
1-2. CC2540 Block Diagram .................................................................................................. 21
1-3. CC2541 Block Diagram................................................................................................... 22
2-1. XDATA Memory Space (Showing SFR and DATA Mapping) ....................................................... 29
2-2. CODE Memory Space .................................................................................................... 29
2-3. CODE Memory Space for Running Code From SRAM .............................................................. 29
2-4. Interrupt Overview......................................................................................................... 45
3-1. External Debug Interface Timing ........................................................................................ 54
3-2. Transmission of One Byte................................................................................................ 54
3-3. Typical Command Sequence—No Extra Wait for Response........................................................ 55
3-4. Typical Command Sequence. Wait for Response .................................................................... 56
3-5. Burst Write Command (First 2 Bytes)................................................................................... 58
4-1. Clock System Overview .................................................................................................. 68
6-1. Flash Write Using DMA................................................................................................... 78
8-1. DMA Operation ............................................................................................................ 97
8-2. Variable Length (VLEN) Transfer Options ............................................................................. 99
9-1. Free-Running Mode ..................................................................................................... 108
9-2. Modulo Mode ............................................................................................................. 109
9-3. Up/Down Mode........................................................................................................... 109
9-4. Output Compare Modes, Timer Free-Running Mode ............................................................... 112
9-5. Output Compare Modes, Timer Modulo Mode....................................................................... 113
9-6. Output Compare Modes, Timer Up/Down Mode..................................................................... 114
9-7. Block Diagram of Timers in IR-Generation Mode.................................................................... 116
9-8. Modulated Waveform Example ........................................................................................ 116
9-9. IR Learning Board Diagram ............................................................................................ 117
11-1. Sleep Timer Capture (Example Using Rising Edge on P0_0) ..................................................... 135
12-1. ADC Block Diagram ..................................................................................................... 138
14-1. Basic Structure of the Random-Number Generator ................................................................. 150
15-1. Message Authentication Phase Block B0 ............................................................................ 155
15-2. Authentication Flag Byte ................................................................................................ 155
15-3. Message Encryption Phase Block ..................................................................................... 156
15-4. Encryption Flag Byte .................................................................................................... 156
19-1. Analog Comparator ...................................................................................................... 176
20-1. Block Diagram of the I
2
C Module ...................................................................................... 178
20-2. I
2
C Bus Connection Diagram ........................................................................................... 179
20-3. I
2
C Module Data Transfer............................................................................................... 179
20-4. Bit Transfer on I
2
C Bus.................................................................................................. 180
20-5. I
2
C Module 7-Bit Addressing Format .................................................................................. 180
20-6. I
2
C Module Addressing Format With Repeated START Condition ................................................ 180
20-7. Arbitration Procedure Between Two Master Transmitters.......................................................... 186
20-8. Synchronization of Two I
2
C Clock Generators During Arbitration ................................................. 187
21-1. USB Controller Block Diagram ......................................................................................... 192
21-2. IN/OUT FIFOs ............................................................................................................ 196
23-1. Modulation ................................................................................................................ 227
23-2. I/Q Phases When Transmitting a Zero-Symbol Chip Sequence, t
C
= 0.5 μs..................................... 227
23-3. Schematic View of the IEEE 802.15.4 Frame Format [1]........................................................... 228
23-4. Format of the Frame Control Field (FCF)............................................................................. 228
11
SWRU191C–April 2009–Revised January 2012 List of Figures
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