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23-5. Frame Data Written to the TXFIFO.................................................................................... 230
23-6. TX Flow.................................................................................................................... 231
23-7. Single Transmitted Frame .............................................................................................. 232
23-8. Transmitted Synchronization Header.................................................................................. 232
23-9. FCS Hardware Implementation ........................................................................................ 233
23-10. Single Received Frame and Transmitted Acknowledgement Frame ............................................. 234
23-11. SFD Signal Timing....................................................................................................... 235
23-12. Filtering Scenarios (Exceptions Generated During Reception) .................................................... 237
23-13. Matching Algorithm for Short and Extended Addresses ............................................................ 239
23-14. Interrupts Generated by Source Address Matching ................................................................. 240
23-15. Data in RXFIFO for Different Settings................................................................................. 241
23-16. Acknowledge Frame Format ........................................................................................... 241
23-17. Acknowledgment Timing ................................................................................................ 242
23-18. Command Strobe Timing ............................................................................................... 242
23-19. Behavior of FIFO and FIFOP Signals ................................................................................. 244
23-20. Main FSM ................................................................................................................. 246
23-21. FFT of the Random Bytes .............................................................................................. 247
23-22. Histogram of 20 Million Bytes Generated With the RANDOM Instruction ........................................ 247
23-23. Running a CSP Program................................................................................................ 251
23-24. Example Hardware Structure for the R* Register Access Mode .................................................. 267
25-1. Mapping of Radio Memory to MCU XDATA Memory Space....................................................... 294
25-2. FIFO Pointers............................................................................................................. 294
25-3. PN7 Whitening ........................................................................................................... 305
25-4. CC2500-Compatible Whitening ........................................................................................ 306
25-5. CRC Module .............................................................................................................. 307
25-6. Air Interface Packet Format for Basic Mode.......................................................................... 310
25-7. Air Interface Packet Format for Auto Mode........................................................................... 311
25-8. Bits of 9-Bit Header...................................................................................................... 311
25-9. Bits of 10-Bit Header .................................................................................................... 311
25-10. Structure of Packets in the Rx FIFO................................................................................... 312
25-11. Structure of Packets in the Tx FIFO................................................................................... 313
25-12. Timing of Packets in Rx Tasks......................................................................................... 328
25-13. Timing of Packets in Tx Tasks ......................................................................................... 329
25-14. Complete Appended Packet............................................................................................ 331
12
List of Figures SWRU191C–April 2009–Revised January 2012
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