6.1 I/O Signal Allocations
6.1.2 Output Signal Allocations
6-6
Note: Refer to the following section for details on input signal parameter settings.
14.1 List of Parameters on page 14-2
Example of Changing Input Signal Allocations
The following example shows reversing the P-OT (Forward Drive Prohibit) signal allocated to
CN1-42 and the /P-CL (External Torque Limit) signal allocated to CN1-45.
Refer to the following section for the parameter setting procedure.
5.1.3
Parameter Setting Methods
on page 5-6
Confirming Input Signals
You can confirm the status of input signals on the I/O signal monitor. Refer to the following sec-
tion for information on the I/O signal monitor.
9.2.3 I/O Signal Monitor on page 9-5
6.1.2
Output Signal Allocations
You can allocate the desired output signals to pins 25 to 30 and 37 to 39 on the I/O signal con-
nector (CN1). You set the allocations in the following parameters: Pn50E, Pn50F, Pn510,
Pn512, Pn513, Pn514, and Pn517.
Output signals are allocated as shown in the following table.
Refer to Interpreting the Output Signal Allocation Tables and change the allocations accord-
ingly.
940
A reverse signal (a signal with “/” before the signal abbreviation, such as the /
S-ON signal) is active when the contacts are OFF (open).
A signal that does not have “/” before the signal abbreviation (such as the P-
OT signal) is active when the contacts are ON (closed).
A41
B42
C43
D44
E45
F46
Pn50A = n.2
0 Pn50B = n.
5
Before change
↓↓
Pn50A = n.5
1 Pn50B = n.
2
After change
Parameter
Setting
Pin No. Description
• The signals that are not detected are considered to be OFF. For example, the /COIN (Position-
ing Completion) signal is considered to be OFF during speed control.
• Reversing the polarity of the /BK (Brake) signal, i.e., changing it to positive logic, will prevent
the holding brake from operating if its signal line is disconnected. If you must change the polar-
ity of this signal, verify operation and make sure that no safety problems will exist.
• If you allocate more than one signal to the same output circuit, a logical OR of the signals will
be output.
Important