*SRE<enable_value>
*SRE?
Service Request Enable. Enables bits in the enable register for the Status Byte Register group. An enable register
defines which bits in the event register will be reported to the Status Byte register group. You can write to or read from
an enable register.
Parameter Typical
Return
Decimal sum of the bits in the register, default 0. For example, to enable bit 2 (value 4), bit 3 (value 8),
and bit 7 (value 128), the decimal sum would be 140 (4 + 8 + 128). Default 0.
+24
Enable bits 3 and 4 in the enable register:
*SRE 24
l To enable specific bits, specify the decimal value corresponding to the binary-weighted sum of the bits in the
register. The selected bits are summarized in the "Master Summary" bit (bit 6) of the Status Byte Register. If any
of the selected bits change from 0 to 1, the instrument generates a Service Request signal.
l *CLS clears the event register, but not the enable register. An event register is a read-only register that latches
events from the condition register. While an event bit is set, subsequent events corresponding to that bit are
ignored.
l *PSC (power-on status clear) determines whether Status Byte enable register is cleared at power on. For example,
*PSC 0 preserves the enable register contents through power cycles.
l The Status Byte enable register is not cleared by *RST.
*STB?
Read Status Byte Query. Queries the condition register for the Status Byte Register group and returns a decimal value
equal to the binary-weighted sum of all bits set in the register.
A condition register continuously monitors the state of the instrument. Condition register bits are updated in real time;
they are neither latched nor buffered.
Parameter Typical Return
(none) +40
Read condition register (with bits 3 and 5 set):
*STB?
l Similar to a Serial Poll, but processed like any other instrument command. This register is read-only; bits are not
cleared when read.
l Returns same result as a Serial Poll, but the "Master Summary" bit (bit 6) is not cleared by *STB?.
l Power cycle and *RST clear all bits in the condition register.
160 Agilent Truevolt Series DMM Operating and Service Guide
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