Efinix Titanium - Page 72

Titanium Interfaces User Guide
Signal Direction Clock
Domain
Description
DLY_ENA Input SLOWCLK (Optional) Enable the dynamic delay control or the DPA
circuit, depending on which one is enabled.
DLY_INC Input SLOWCLK (Optional) Dynamic delay control. Cannot be used with
DPA enabled. When DLY_ENA is 1,
1: Increments
0: Decrements
DLY_RST Input SLOWCLK (Optional) Reset the delay counter or the DPA circuit,
depending on which one is enabled.
OUT[9:0] Input SLOWCLK Parallel output data from the core. The width is
programmable.
OUTSLOWCLK Input – Parallel (slow) clock for TX.
OUTFASTCLK Input – Serial (fast) clock for TX.
OUTRST Input SLOWCLK (Optional) Resets the TX serializer.
OE Input – Output enable signal.
LVDS Pads
Table 41: LVDS Pads
Signal Direction Description
P Output Differential pad P.
N Output Differential pad N.
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