9-24 Section 9: Verifying the Model 9500B Accuracy Specification
Final Width = 215mm
8. Other Tables Repeat Items (2) to (7), but for Tables 9.9.2.2,
9.9.2.3 and 9.9.2.4 in turn.
The measurements are now complete.
9.9.2.6 Calculation of Validity Tolerances
1. Introduction
The first part of the verification procedure in sub-section 9.9.1 deals
with verification of amplitude at frequencies below 50kHz, into input
impedance of 50Ω. A DMM in ACV function is used here as the
calibration standard. Unfortunately, the frequency response of DMMs
falls off at frequencies which must be used to verify HF flatness above
1MHz, and so a commonly-used technique employs an RF Power
Meter. Flatness is normally expressed as a voltage relative to that at a
reference frequency of 50kHz, and in our procedure, Tables 9.9.2.1,
9.9.2.2, 9.9.2.3 and 9.9.2.4 are used to register the values at this
reference frequency.
For the flatness verification, each output voltage is measured as power
into 50Ω in an RF Power Meter, and converting power to pk-to-pk
voltage using a formula given in the procedure. This voltage is
compared against the power meter reading at 50kHz, by checking that
it is within validity tolerance limits about the 50kHz value.
To calculate the validity tolerance limits at each verification point, we
must take into account the Total Measurement Uncertainty and the
specified 9500B flatness, with respect to 50kHz. These are combined
using an RSS calculation..
2. Example: Calculation of Validity Tolerance at 10MHz
• From the Power Meter Specification, let us say that its Total
Measurement Uncertainty (Power) at 10MHz, including the Sensor
uncertainty, is: ±1.4%.
• But this is a power uncertainty, and the pk-pk voltage uncertainty
will be half: ±0.7%.
• With this we must combine (by RSS Method) the 9500B pk-pk
voltage flatness specification. At 10MHz, the 9500B specification
relative to 50kHz is ±1.5%.
Validity Tolerance = √[(0.007)
2
+ (.015)
2
]
= ±0.01655 = ±1.655%
• We must now multiply this by the Reference value at 50kHz, and
obtain the higher limit at 10MHz by adding the Validity Tolerance
to the 50kHz Reference value. The lower limit at 10MHz is found
by subtracting the Validity Tolerance from the 50kHz Reference
value.
9.9.2.4 Verification Setup
1. Connections Ensure that the 9500B is connected to the RF Power
Meter as shown in Fig. 9.9.2.1, and that both
instruments are powered on and warmed up.
2. 9500B Ensure that the 9500B is in MANUAL mode and
then select the Sine function (
key). Select the
required output Signal Channel (50Ω Load), Trigger
Channel and Trigger Ratio (if required).
9.9.2.5 Verification Procedure
1. Copy the Tables 9.9.2.1, 9.9.2.2, 9.9.2.3 and 9.9.2.4.
2. Starting with Table 9.9.2.1, follow the correct sequence of
verification points as shown on the table, and carry out operations
(3) to (7) at the verification points on the table.
3. 9500B a. Set the Output Volts p-p as required for the
verification points on the table.
b. Set Frequency to 50kHz.
c. Set Output ON.
4. Power Meter Select a power range which gives an on-scale
reading (the example Power Meter auto-ranges to
accommodate the input power).
5. 'Ref' a. Measure the 9500B output power at 50kHz and
calculate the Pk-Pk value of 9500B output
voltage into 50Ω:
Pk-Pk Voltage = 20√(power into 50Ω)
b. Record the result in the 'Measured p-p Voltage
at 50kHz' column on the copy of the Table.
6. Flatness a. Set the 9500B Frequency to the first '
SF' point
in the table.
b. measure the 9500B output power and calculate
the Pk-Pk value of 9500B output voltage into
50Ω:
Pk-Pk Voltage = 20√(power into 50Ω)
c. Record the result in the 'Measured p-p Voltage
for Flatness Check' column for the verification
point on the copy of the Table.
d. Set the 9500B Frequency to the next '
SF' point
in the table, and repeat operations (b) and (c).
e. Repeat operation (d) for all other '
SF' points in
the table available for the UUT variant type.
7. 9500B Set Output OFF.
9.9.2 Verifying the Levelled Sine Function: Flatness (Contd.)
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