This section will explain the practical use of this module. After system reset, the I²C module has
to be initialised as follows:
Set SCL frequency from system clock using Frequency Divider Register (IBFD),
Define its slave address by setting I²C Bus Address Register
Clear MDIS field in IBCR to enable the I²C interface.
Configure IBCE as needed to select master/slave, transmit/receive, interrupt enable etc.
Configure IBIC if needed.
Once the initialisation is completed, for master transmission, the first thing to be done is START
signal generation. This signal’s generation is automated into this module with the selection of
transmit and master mode, if the bus has been free for a while. Example:
Wait for IBB flag to be cleared (bus free & ready to transmit)
Set transmit and master mode on IBCR (start condition is prepared)
Write calling address in to the data register IBDR
Wait for IBB flag to be set (start signal and slave address are sent)
During a transfer, use the interrupt handler to check status register and take action depending
on master/slave and transfer/receive (see the last paragraph of this section).
For master transmit situation a STOP signal is generated when the device goes into slave mode.
In a master receive situation, master has to tell the receiver that it is terminating the transfer by
not acknowledging the last byte of data.
For generating a repeated START signal instead of a STOP, you can simply set the repeated start
bit of the control register and write the new calling address in to the data register.
The reference manual suggests the use of the interrupt routine illustrated on the following figure
for managing transmission and STOP signal generation phase of the communication. This
routine takes action according to master/slave, TX/RX situation. A driver can be built upon a
handler like this with some initialisation and transfer start routines.
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