Freescale Semiconductor MPC5604B - GPIO: General Purpose Input;Output

Figure 47 : eMIOS A, B and Alt A Register R/W (R.M. Rev8 – Table 24-16)
Figure 48 : An eMIOS Channel’s Block Diagram
In the following sections, we will study different modes of operations and how registers A and
B behave in each one of them.
1.2.
GPIO: General Purpose Input/Output
In General Purpose Input/Output mode all input capture, output compare and timing functions
are disabled. Registers A and B hold the same value. All channels are in this mode by default and
have to go through this mode when a mode change occurs.
Counter Bus
Select (BSL)
Internal
Counter
Prescaler
UCPRE
UCPREN
eMIOS Internal
Counter Clock
Secondary Counter Bus
(B,C…)
Primary Counter Bus A
Input
Filter
IF, FCK
Edge Detect
B1
B2
A1
A2
Comparator
A
Comparator
B
Finite State
Machine
MODE
FORCMA
FORCMB
EMIOS_OUDR
EMIOS_OUDR
SET
R/W
R/W
CLR
Flip-Flop
EDPOL
EDSEL
OUT
UCOUT
UCIN