Freescale Semiconductor MPC5604B - 2. STM: System Timer Module; 3. PIT: Periodic Interrupt Timer

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Chapter 3
INTC: Interrupt Controller
1.
Introduction
The core of MPC5604B (e200z0h) is associated with registers called Interrupt Vector Offset
Register (IVOR), which handles different kinds of exceptions that might occur during runtime.
Different kinds of core exceptions are handled by different IVORs. IVOR4 is the one used for
interrupt handling.
Figure 29 : Interrupt Requests Handling by INTC in Software Vector Mode (Freescale Lecture)
The Interrupt Controller (INTC) is a module that is used for Interrupt Service Requests (ISR)
management. In software vector mode
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, ISRs coming from peripherals trigger IVOR4 exceptions.
This exception branches to INTC handling functions which saves current register and program
counter (Prologue), then jumps to the ISR Vector Table where the vector associated to the
particular ISR allows jumping to the ISR handler(written by the user). The handler clears the ISR
flag and returns back to the INTC’s handler routine which restores core’s status (Epilogue).
Figure 30 : ISR Handling (SW mode) (Freescale Lecture)
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In hardware mode, each handler has to write its own Prologue and Epilogue and their IVORs are
separate. It will be briefly explained at the end of the chapter.