with standard I²C bus specifications simply by setting open drain option for the SDA/SCL pads in
SIUL.
This module is designed to operate in Standard or Fast Mode I²C but it is capable of going at
baud rates up to module_clock/20 as long as the bus can support it with the right pull-up device.
This module brings simplicity in implementing I²C bus, electrical characteristics are met,
different phases of the transfer like the start signal, stop signal, acknowledge and byte transfer
are handled automatically. Only thing the user has to do is to bring them together in an interrupt
handler in a way that matches their needs.
This module has six 8-bit registers, one for baud-rate setting, one for module control, two for
status management and two others for address and data.
Frequency setting
The baud rate of this module can be configured using the I²C Bus Frequency Divider Register
(IBFD), who has an 8-bit field called IBC (I-Bus Clock Rate) which can be decomposed in three
different fields used for calculating the prescaler values. In this document we will not explain
those calculations, simply refer to the appendix I²C Baud Rate Prescaler Values for getting
different clock cycle numbers related to a IBC value.
The baud-rate is =
__
. The other parameters can be used to calculate SDA hold,
SCL start and stop hold timings as shown in the figure below.
With
_
=
__
,
_
=
__
and
_
=
__
.
Example with a 64MHz peripheral clock frequency for getting 400kbps baud rate.
We need SCL_divider = 64000/400 = 160, and SDA_hold < 0.9*64 = 57 clocks,
SCL_start/stop_hold > 0.6*64= 39 clocks.
IBC=0x1D fits as well as 0x20, 0x54, 0x58, 0x87 and 0x8B.
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