Freescale Semiconductor MPC5604B - Chapter 7 CTU: Cross Triggering Unit; 1. Introduction

2.
ADC Configuration
2.1.
Pad Configuration
Using the SIUL module, the software has to set the APC bit of the PCR register of a pad with ADC
functionality, there is no need to bother with other fields or alternate functions.
2.2.
General Registers
In this section we will talk about ADC module’s principal configuration registers.
Figure 71 : Main Configuration Register (R.M. Rev8 – Fig. 25-8)
The Main Configuration Register (MCR) has the following fields:
 Overwrite enable (OWREN): set this bit to enable converted data to be overwritten
by new conversion. Otherwise new data is discarded until the current data is read.
 Write left/right aligned (WLSIDE): changes the DATA fields’ position in the CDR
register. (NOTE: always leave at 0 if the register definition header file is used in C).
 MODE: if cleared, one shot mode is selected; else, scan mode is selected.
 Normal Start conversion (NSTART): starts a normal mode conversion when set (see
sections above).
 Injection external trigger enable (JTRGEN): Injection external trigger enable (set to
enable).
 Injection trigger edge selection (JEDGE): clear to trigger at a falling edge, set for
selection a rising edge.
 Injection start (JSTART): setting this bit will start the injection mode. Resetting it
won’t stop it. (See sections above).
 CTU conversions enable (CTUEN): CTU triggered conversions are enabled if set. (See
next chapter for more information).
 Analog clock select (ADCLKSEL): if cleared, ADC clock frequency is half peripheral set
clock frequency. Otherwise it is equal to the peripheral set clock frequency.
 Abort chain (ABOTCHAIN): when set, aborts the ongoing sequence.
 Abort conversion (ABORT): when set, aborts only the ongoing conversion.
 Auto-clock-off enable (ACK0): set to enable this power mode.
 Power-down enable (PWDN): set to request a power down.