This register’s main fields are:
TWRN_INT: TX Warning Interrupt Flag; if WRN_EN bit is set in MCR, then this flag is
raised whenever TX Error Counter goes from <96 to 96. If WRN_MSK bit is set in
CTRL then an interrupt is generated. It is cleared by writing ‘1’. Similarly for RWRN_INT
but for RX.
BIT1_ERR: Bit1 error is set when an inconsistence occurs between transmitted and
received bit in a message such that a bit sent as recessive is received as dominant. (a
special case of BIT ERROR).
BIT0_ERR: very similar to BIT1_ERR but for the case where a bit send as dominant is
received as recessive.
ACK_ERR: this bit is set if an ACK error has occurred since the last read of this register.
CRC_ERR: this bit is set if an CRC error has occurred since the last read of this register.
FRM_ERR: this bit is set if a form error has occurred since the last read of this register.
STF_ERR: this bit is set if a stuffing error has occurred since the last read of this register.
TX_WRN: this bit is set if TX_ERR_COUNTER 96. RX_WRN is similar.
IDLE: this bit is set if the CAN bus is now idle.
TXRX: if set, Flex CAN is transmitting a message, else it is receiving a message. This bit
has no meaning if IDLE is set.
FLT_CONF: indicates the confinement state of the module: 00: Error Active, 01, Error
Passive, 1x: Bus Off.
BOFF_INT: bus off interrupt. This bit is set when FlexCAN goes into Bus Off state
(depending on counters). An interrupt is generated if the mask in CTRL is set. Write ‘1’ to
clear.
ERR_INT: Error interrupt, if at least one of the x_ERR bits is set, this flag is raised. If the
mask in CTRL is set, an interrupt is generated. Write ‘1’ to clear the flag.
There is an Error Counter Register (ECR) which has two 8-bit fields for RX_ERR_COUNTER and
TX_ERR_COUNTER. There are different error flags/interrupts raised depending on values of
these:
If one of the counters is 128, then module goes into Error Passive state,
While the module is in Error Passive state and one of the counter goes below 127, then
Error Active state is active.
If TX counter is greater than 255, then the module goes to Bus Off state and counter is
reset.
While in Bus Off state, FlexCAN stops transmitting and waits for 128 valid occurrences of
11 consecutive recessive bits.
RX_ERR_COUNTER is no longer incremented if it goes over 127. If after a successful
reception, the counter goes between 119 and 127 then Error Active state is active.
A pair of registers that can be useful are Interrupt Flags Register 2 and Interrupt Flags Register 1
(or IFRH and IFRL). These register together contain 64 flag bits for each one of the Message
Buffers. A flag is raised if the corresponding buffer has successfully made a reception or
transmission. There is also a pair of mask registers for these flags (IMRH and IMRL). It should be
noted that in FIFO mode, flag bits BUF5I to BUF7I have different meanings. BUF7I is FIFO
To Next Page
Loading...
