Figure 33. Trace Memory Save/Recall 112
Figure 34. Setup Memory 113
Figure 35. Relationship Between Time base and Analyzer Functions 129
Figure 36. Acquisition Memory 131
Figure 37. Memory Bar 132
Figure 38. Single Acquisition, Time Reference Center, Positive
Delay of 75 µs 134
Figure 39. Panning the Display to View the Start of Acquisition 135
Figure 40. Single Acquisition, Time Reference Right, Negative
Delay of 80 µs 136
Figure 41. Panning the Display to View the Trigger Point 137
Figure 42. DC and Low-Frequency Probe Equivalent Circuit 139
Figure 43. High-Frequency Probe Equivalent Circuit 140
Figure 44. Impedance versus Frequency for Both Probe Circuit Models 140
Figure 45. Common Mode Input Voltage Model 141
Figure 46. Glitch Display 144
Figure 47. Aliasing 144
Figure 48. Reconstruction of Waveform with Glitch Capture 145
Figure 49. Waveform Display with Sampling Rate Too Low 146
Figure 50. Waveform Display with Sufficient Sampling Rate 147
Figure 51. Data Output Relative to Clock 148
Figure 52. 8-by-2 Connector Setup 156
Figure 53. 1-by-2 Connector Setup 157
Figure 54. Power Supply Adjustment 161
Figure 55. Display Adjustment 163
Figure 56. Threshold Test Setup 171
Figure 57. Time Interval Accuracy Setup 174
Figure 58. Front Panel Removal 184
Figure 59. Unhooking the Power Switch Shaft 187
Figure 60. Exploded View of Logic Analyzer 192
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