Intel SC5650BCDP Technical Product Specification

Functional Architecture Intel
®
Server Board S5500BC TPS
Intel order number: E42249-009 Revision 1.8
28
 The Independent Channel Mode is the default maximum performance mode preferred
for Intel
®
Xeon
®
processor 5500 series and 5600 series based platforms.
 Socket1 usually has precedence over socket 2 in determining the possible RAS modes.
 The sockets are autonomous and capable of being independently initialized. However,
the minimal upgrade for socket 2 is DIMM_D1 in Independent Channel Mode.
 Minimal upgrade for Channel Mirror mode is {D1, E1}. If this mode fails, then the
Independent channel mode is used across the sockets.
 If an installed DDR3 DIMM has faulty or incompatible SPD data, it is ignored during the
memory initialization and therefore essentially disabled by the BIOS. If the DDR3 DIMM
has no or missing SPD information, the BIOS ignores the DIMM and the slot is marked
as empty.
 The DDR3 DIMM populated in slot DIMM_B1 of socket1 determines the RAS mode of
the system. If the DIMM_A1 and DIMM_B1 are not identical, then the system falls back
to Independent Channel Mode.
 The minimal memory population possible is DIMM_A1. In this configuration, the system
operates in Independent Channel Mode. No RAS is possible.
 The minimal memory population for Channel Mirroring Mode is {A1, B1}.
 Memory population on channel A and channel B of socket 1 should be identical to
enable Channel Mirroring Mode. Channel D and channel E of socket 2 should also be
identical.
 If the DDR3 DIMMs on adjacent channels of a socket are not identical in mirroring, the
DIMMs on the higher slots are disabled.
 DIMM parameters and matching requirements for memory RAS are specific to each
socket.
 When one socket fails the DIMM matching on the adjacent channels for the RAS
configuration selected in Setup, the BIOS configures all DDR3 Channels to
Independent mode.
 DDR3 DIMMs on the same channel but adjacent slots do not need to be identical.
3.2.4 Memory RAS Features
The Intel
®
server boards S5500BC supports the following memory RAS features:
 Channel Independent Mode
 Channel Mirroring Mode
 Demand and Patrol Scrub
The Intel
®
Xeon
®
processor 5500 series and 5600 series offer memory RAS at the channel level.
Mirroring occurs at the channel level. Channel B mirrors channel A. All DIMM matching
requirements are on a slot-to-slot basis on adjacent channels. To enable Mirroring, the
corresponding slots on channels A and B must have DIMMs with identical parameters. DIMMs
on adjacent slots on the same channel are not required to have identical parameters.
When installing memory, you must populate first the memory slot that is the farthest away in the
channel for each processor (refer to the Channel Slots Configuration figure), even for
Independent Channel mode. Therefore, you cannot populate/use DIMM_A2 if DIMM_A1 is
empty.

Intel SC5650BCDP Specifications

General

Brand	Intel
Model	SC5650BCDP
Category	Server
Language	English