Platform Management Intel
®
Server Board S5500BC TPS
Intel order number: E42249-009 Revision 1.8
secondary IPMB. The BMC does not own any platform event filters or traps for NM-related
events. You should configure these events in the NM by server management software.
4.4.3 External Communications Link
standard IPMI Send Message commands. See the command bridging section in the Intelligent
Platform Management Interface Specification Second Generation v2.0 for more information.
All NM-related IPMB transactions use the secondary IPMB. This is a private I
2
C bus that is only
accessible by the BMC and ME. Please see the appropriate platform appendix for channel and
bus number information.
4.4.4 Alerting
two different methods to send an alert. Each method is outlined in the following sections.
Fault Events
Alerts that signify fault conditions and should be recorded in the system SEL are sent to the
BMC by the ME using the IPMI Platform Event Message command. The BMC deposits
these events into the SEL. The
features to send that event out as an IPMI LAN alert, directed to the SW application over
the LAN link.
Informational Events
Alerts that provide useful notification to the external SW for NPTM management but do not
represent significant fault conditions and do not need to be entered in the SEL are sent to
the BMC using the IPMI Alert Immediate command. This requires the external SW
application provide the NM on the ME with the alert destination and alert string information
needed to properly form and send the alert. The external SW must first properly configure
the alert destination and string in the BMC LAN configuration using standard IPMI
commands, then provide the associated selectors to the BMC using the Set Node Manager
Alert Destination OEM command.
4.4.5 System Information Passed to ME and POST Complete Notification
The BIOS sends the BMC the following information during POST:
Number of supported P-states
Number of supported T-states
Platform Info (data from processor MSR 0CEh)
TDP value per CPU
When the BMC detects that POST has completed, the BMC passes on the BIOS-provided
system information to the ME. As part of this command transaction to the ME, the BMC also
provides the total number of installed CPUs, the Icc_TDC value for each CPU (retrieved by the
BMC via PECI), and a notification that POST has completed.