Intel
®
Server Board S5500BC TPS Power and Environmental Specifications
Revision 1.8 Intel order number: E42249-009 111
Table 71. Output Voltage Timing
Output voltage rise time from each main output.
All main outputs must be within regulation of each other
within this time.
All main outputs must leave regulation within this time.
*The 5 VSB output voltage rise time shall be from 1.0 ms to 25.0 ms
Figure 46. Output Voltage Timing
Table 72. Turn On/Off Timing
Delay from AC applied to 5VSB within regulation.
Delay from AC applied to all output voltages within regulation.
Time all output voltages stay within regulation after loss of
AC. Measured at 75% of maximum load.
Delay from loss of AC to de-assertion of PWOK. Measured at
75% of maximum load.
Delay from PSOn
#
active to output voltages within regulation
limits.
Delay from PSOn
#
deactive to PWOK being de-asserted.