Intel SC5650BCDP Technical Product Specification

Intel
®
Server Board S5500BC TPS Functional Architecture
Revision 1.8 Intel order number: E42249-009 27
 Sockets are self-contained and autonomous. However, all RAS Error Management
configurations in the BIOS setup are applied commonly across sockets.
Figure 16. Channel slots Configuration
3.2.3 Memory Upgrade Guidelines
Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the
following factors:
 The current RAS mode of operation.
 The existing DDR3 DIMM population.
 The DDR3 DIMM characteristics.
 The optimization techniques used by the Intel
®
Xeon
®
processor 5500 series and 5600
series to maximize memory bandwidth.
In Independent Channel Mode all DDR3 channels operate independently. Slot-to-slot DIMM
matching is not required across channels. For example, DIMM_A1 and DIMM_B1 do not have
to match in terms of size, organization, and timing. DIMMs in a channel can be a different size
and organization, but they will operate at the maximum common frequency. You can use
Independent Channel Mode to support a single DIMM configuration in channel A and Single
Channel Mode.
You should observe the following general rules when selecting and configuring memory to
obtain the best performance from the system.

Intel SC5650BCDP Specifications

General

Brand	Intel
Model	SC5650BCDP
Category	Server
Language	English