Intel SC5650BCDP Technical Product Specification

Intel
®
Server Board S5500BC TPS Functional Architecture
Revision 1.8 Intel order number: E42249-009 23
and groups DIMMs on the board into an autonomous RAS memory. The server board is
designed to support a DDR3-based memory subsystem with eight DIMM slots.
The following configurations are not supported, validated or recommended:
 Mixing of RDIMMs and UDIMMs is not supported
 Mixing of memory type, size, speed and/or rank has not been validated and is not
supported
 Mixing memory vendors has not been validated and is not recommended
 Non-ECC memory has not been validated and is not supported in a server environment
Note: Mixed memory is not tested or supported. Non-ECC memory is not tested and is not
recommended for use in a server environment
Table 7. Supported DDR3 Memory
DIMM Capacity
DRAM Rank and
Organization
Memory Speed (MT/s)
RDIMM/UDIMM
DRAM capacity
1 GB
1R x 8
800/1066/1333
RDIMM/UDIMM
1Gb
2 GB
2R x 8
800/1066/1333
RDIMM/UDIMM
1Gb
2 GB
1R x 4
800/1066/1333
RDIMM/UDIMM
1Gb
4 GB
4R x 8
800/1066
RDIMM
1Gb
4 GB
2R x 8
800/1066
UDIMM
2Gb
The latest supported memory configurations lists are available at:
http://serverconfigurator.intel.com/configure-
memory.aspx?id=MTY2MyMxLDI1MTYjMSwyNjIwIzIsMjUzMiMx
The BIOS can configure the memory controller dynamically in accordance with the available
DDR3 DIMM population and the selected RAS (reliability, availability, and serviceability) mode
of operation.
3.2.1.1 CPU Cores, QPI Links and DDR3 Channels Frequency Configuration
The Intel
®
Xeon
®
5500 series or 5600 series processor connects to other Intel
®
Xeon
®
5500
series or 5600 series processors and Intel
®
5500 IOH through the Intel
®
QPI link interface. The
frequencies of the processor cores and the QPI links of Intel
®
Xeon
®
5500 series and 5600
series processor are independent from each other. There are no gear-ratio requirements for the
Intel
®
Xeon
®
Processor 5500 Series and 5600 series.
Intel
®
5500 IOH supports 4.8 GT/s, 5.86 GT/s, and 6.4 GT/s frequencies for the QPI links.
During QPI initialization, the BIOS configures both endpoints of each QPI link to the same
supportable speeds for the correct operation.
During memory discovery, the BIOS arrives at a fastest common frequency that matches the
requirements of all components of the memory system and then configures the DDR3 DIMMs
for the fastest common frequency.

Intel SC5650BCDP Specifications

General

Brand	Intel
Model	SC5650BCDP
Category	Server
Language	English