Intel SC5650BCDP

Table of Contents Intel
®
Server Board S5500BC TPS
Intel order number: E42249-009 Revision 1.8
iv
Table of Contents
1. Introduction .......................................................................................................................... 1
1.1 Server Board Use Disclaimer .................................................................................. 1
2. Product Overview ................................................................................................................. 2
2.1 Feature Set .............................................................................................................. 2
2.2 Server Board Layout ................................................................................................ 4
2.2.1 Server Board Connector and Component Layout .................................................... 4
2.2.2 Server Board Mechanical Drawing .......................................................................... 6
2.2.3 Intel
®
Light-Guided Diagnostic LED Locations ....................................................... 13
2.2.4 External I/O Connector Locations .......................................................................... 14
3. Functional Architecture ..................................................................................................... 15
3.1 Processor Subsystem ............................................................................................ 15
3.1.1 Intel
®
QuickPath Interconnect (QPI) ...................................................................... 16
3.1.2 Processor Population Rules .................................................................................. 17
3.1.3 Multiple Processor Initialization ............................................................................. 19
3.1.4 Turbo Mode ........................................................................................................... 20
3.1.5 Intel
®
Hyper-Threading Technology (Intel
®
HT) ..................................................... 20
3.1.6 Enhanced Intel
®
SpeedStep
®
Technology (EIST) .................................................. 20
3.1.7 Core Multi-Processing ........................................................................................... 20
3.1.8 Independent Loading Mechanism (ILM) Back Plate Design Support .................... 21
3.2 Memory Subsystem ............................................................................................... 22
3.2.1 Supported Memory ................................................................................................ 22
3.2.2 DIMM Population Requirements ............................................................................ 26
3.2.3 Memory Upgrade Guidelines ................................................................................. 27
3.2.4 Memory RAS Features .......................................................................................... 28
3.2.5 Channel Mirroring Mode ........................................................................................ 29
3.2.6 Demand and Patrol Scrub ..................................................................................... 29
3.3 Intel
®
I/O Hub (IOH) 5500 chipset .......................................................................... 29
3.3.1 PCI Express* Gen 2 ............................................................................................... 30
3.3.2 Enterprise South Bridge Interface (ESI) Features ................................................. 30
3.3.3 Controller Link (M-Link) ......................................................................................... 30
3.3.4 Management Engine (ME) ..................................................................................... 30