Mitsubishi Electric MELSEC-Q Series - Page 267

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CHAPTER 7 PROCESSING TIME
7
7.5 Cyclic Data Retention Time for System Switching in a Redundant System
(2) When a stop error occurs in the control system CPU, System switching
instruction is executed, system switching is executed from the programming
tool, or system switching is requested from another network module
*1 For details, refer to the following.
QnPRHCPU User's Manual (Redundant System)
Th = Tsw + SS [ms]
Th: Cyclic data retention time
Tsw: System switching time of Redundant CPU
*1
SS: Sequence scan time of Redundant CPU
*1
1
0)
1)
2
3
4
5
2) 3)
4)
0)
1)
2)
3)
4)
System A
CPU scan time
Data sent from
station No.1 to
another station
System A
System B
System B
CPU scan time
Data sent from
station No.2 to
another station
Data received
at another
station from
station No.1 or 2
Control system
Control system
Standby system
Standby system
System switching time
Cyclic transmission
delay time
Cyclic transmission delay time
Cyclic data retention time
Execution of system
switching instruction