76
4.1.5 Assurance of cyclic data integrity
This function allows cyclic data integrity to be assured in units of 32 bits or stations.
: Data assured, ×: Data not assured
● Link scans are performed "asynchronously" with link refresh.
Therefore, when the following cyclic data of 32 bits or more are handled, new and old data may be mixed in units of 16
bits depending on the link refresh timing.
• Floating point data
• Present value or command speed value of a positioning module
● Even if latched device (listed in "CPU side device" in the table below) data are cleared to 0 by a sequence program at
power-on or reset of the CPU module, the latched data may be output depending on the timing of link scan and link
refresh.
For how to prevent output of latched device data, perform "Method for disabling output" listed in the table below.
*1 For how to set an initial device value, refer to the following.
User's manual (Function Explanation, Program Fundamentals) for the CPU module used
Assurance of cyclic data
integrity
Link refresh
Direct access to link devices
Direct access
32-bit data assurance
Station-based block data assurance ×
Interlock program
CPU side device Method for disabling output
Latch relay (L)
Clear the value of the device to 0 using the initial device
value
*1
.
File register (R, ZR)
Extended data register (D)
(For Universal model QCPU only)
Delete all latch range settings.Extended link register (W)
(For Universal model QCPU only)
Device in the latch range
END0END0 END0END0
Sequence scan
Link scan
Link refresh Link refresh Link refresh
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