Motorola MC68020 - Page 106

5- 58 M68020 USER’S MANUAL MOTOROLA
CLK
A31–A0
FC2–FC0
R/W
ECS
OCS
AS
DS
DSACK0
DBEN
D31–D0
IPL2–IPL0
DSACK1
S0
S2
Sw
S4
S0
S2
Sw
S4
SIZ1–SIZ0
BERR
HALT
WRITE WITH BERR ASSERTED
INTERNAL
P
ROCESSIN
G
STACK WRITE
**
**
**
*
*
For the MC68EC020, A23–A0.
This signal does not apply to the MC68EC020.
**
Figure 5-39. Late Bus Error with
DSACK1/DSACK0