Motorola MC68020 - Page 14

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0
xviii M68020 USER’S MANUAL MOTOROLA
LIST OF TABLES
Table Page
Number Title Number
1-1 Addressing Modes ........................................................................................... 1-9
1-2 Instruction Set .................................................................................................. 1-11
2-1 Address Space Encodings............................................................................... 2-4
3-1 Signal Index ..................................................................................................... 3-3
3-2 Signal Summary............................................................................................... 3-8
5-1 DSACK1/DSACK0 Encodings and Results .................................................... 5-5
5-2 SIZ1, SIZ0 Signal Encoding............................................................................. 5-7
5-3 Address Offset Encodings ............................................................................... 5-7
5-4 Data Bus Requirements for Read Cycles ........................................................ 5-8
5-5 MC68020/EC020 Internal to External Data Bus Multiplexer—
Write Cycles ................................................................................................... 5-9
5-6 Memory Alignment and Port Size Influence on Read/Write Bus Cycles.......... 5-20
5-7 Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports............. 5-22
5-8
DSACK1/DSACK0, BERR, HALT Assertion Results..................................... 5-54
6-1 Exception Vector Assignments ........................................................................ 6-3
6-2 Tracing Control ................................................................................................ 6-9
6-3 Interrupt Levels and Mask Values.................................................................... 6-12
6-4 Exception Priority Groups ................................................................................ 6-18
6-5 Exception Stack Frames.................................................................................. 6-26
7-1 cpTRAPcc Opmode Encodings........................................................................ 7-16
7-2 Coprocessor Format Word Encodings............................................................. 7-18
7-3 Null Coprocessor Response Primitive Encodings............................................ 7-32
7-4 Valid Effective Address Field Codes................................................................ 7-36
7-5 Main Processor Control Register Select Codes............................................... 7-41
7-6 Exceptions Related to Primitive Processing .................................................... 7-53
8-1 Examples 1–4 Instruction Stream Execution Comparison............................... 8-8
8-2 Instruction Timings from Timing Tables ........................................................... 8-11
8-3 Observed Instruction Timings .......................................................................... 8-11