Motorola MC68020 - Page 304

INDEX-4 M68020 USER’S MANUAL MOTOROLA
— L —
Long-Word Operand, 5-10, 5-14
Long-Word Read Cycle, 5-26
Long-Word Write Cycle, 5-33
— M —
M-Bit (SR), 1-7, 2-2
Main Processor Detected
Address Error, 7-57
Bus Faults, 7-57
cpTRAPcc Instruction Traps, 7-55
Exceptions, 7-52
F-Line Emulator Exception, 7-54
Format Error, 7-57
Interrupts, 7-56
Privilege Violations, 7-55
Protocol Violation, 7-52
Trace Exception, 7-55
Master Stack Pointer (MSP), 1-4, 2-2
Maximum Ratings, 10-1
MC68881/MC68882 Floating-Point Coprocessors,
9-1
Memory Interface, 9-11
Misaligned
Operand, 5-6, 5-14, 8-2
Transfer, 5-1, 5-5
Module, 9-14
Module Call, 9-18
Module Return, 9-19
Module Stack Frame, 9-16
MOVE Instruction, 8-20
MOVE SR Instruction, 8-3
MOVEA Instruction, 8-20
MOVEC Instruction, 4-3
— N —
Nonmaskable Interrupt, 6-12
NOP Instruction, 5-62, 8-3
Normal Processing State, 2-1
— O —
OCS Signal, 3-4, 5-3
Ordering Information
MC68020, 11-1
MC68EC020, 11-1
Overlap, 8-3
— P —
Package Dimensions
MC68020 FC Suffix, 11-6
MC68020 FE Suffix, 11-7
MC68020 RC Suffix, 11-3
MC68020 RP Suffix, 11-4
MC68EC020 FG Suffix, 11-11
MC68EC020 RP Suffix, 11-9
Pin Assignment
MC68020 FC Suffix, 11-5
MC68020 FE Suffix, 11-5
MC68020 RC Suffix, 11-2
MC68020 RP Suffix, 11-2
MC68EC020 FG Suffix, 11-10
MC68EC020 RP Suffix, 11-8
Port Size, 5-1, 5-5, 5-21, 9-5
Power Supply, 3-7, 9-9
Primitive, 7-4, 7-27
Busy Response Primitive, 7-30
CA Bit, 7-29
DR Bit, 7-29
Evaluate and Transfer Effective Address
Primitive, 7-35
Evaluate Effective Address and Transfer Data
Primitive, 7-35
Format, 7-28
Null Coprocessor Response Primitive, 7-31
PC Bit, 7-29
Supervisor Check Primitive, 7-33
Take Address and Transfer Data Primitive,
7-39
Take Midinstruction Exception Primitive, 7-47
Take Postinstruction Exception Primitive,
7-48
Take Preinstruction Exception Primitive, 7-45
Transfer from Instruction Stream Primitive,
7-34
Transfer Main Processor Control Register
Primitive, 7-41
Transfer Multiple Coprocessor Registers
Primitive, 7-42
Transfer Multiple Main Processor Registers
Primitive, 7-42
Transfer Operation Word Primitive, 7-33
Transfer Single Main Processor Register
Primitive, 7-40