Motorola MC68020 - Page 6

9/29/95 SECTION 1: OVERVIEW UM Rev.1.0
x M68020 USER’S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 7
Coprocessor Interface Description
7.1 Introduction ............................................................................................. 7-1
7.1.1 Interface Features ............................................................................... 7-2
7.1.2 Concurrent Operation Support ............................................................ 7-2
7.1.3 Coprocessor Instruction Format.......................................................... 7-3
7.1.4 Coprocessor System Interface ............................................................ 7-4
7.1.4.1 Coprocessor Classification .............................................................. 7-4
7.1.4.2 Processor-Coprocessor Interface.................................................... 7-5
7.1.4.3 Coprocessor Interface Register Selection ....................................... 7-6
7.2 Coprocessor Instruction Types ............................................................... 7-7
7.2.1 Coprocessor General Instructions....................................................... 7-8
7.2.1.1 Format ............................................................................................. 7-8
7.2.1.2 Protocol............................................................................................ 7-9
7.2.2 Coprocessor Conditional Instructions.................................................. 7-10
7.2.2.1 Branch on Coprocessor Condition Instruction ................................. 7-12
7.2.2.1.1 Format .......................................................................................... 7-12
7.2.2.1.2 Protocol........................................................................................ 7-12
7.2.2.2 Set on Coprocessor Condition Instruction ....................................... 7-13
7.2.2.2.1 Format .......................................................................................... 7-13
7.2.2.2.2 Protocol........................................................................................ 7-14
7.2.2.3 Test Coprocessor Condition, Decrement, and Branch Instruction... 7-14
7.2.2.3.1 Format .......................................................................................... 7-14
7.2.2.3.2 Protocol........................................................................................ 7-15
7.2.2.4 Trap on Coprocessor Condition Instruction ..................................... 7-15
7.2.2.4.1 Format .......................................................................................... 7-15
7.2.2.4.2 Protocol........................................................................................ 7-16
7.2.3 Coprocessor Context Save and Restore Instructions ......................... 7-16
7.2.3.1 Coprocessor Internal State Frames................................................. 7-17
7.2.3.2 Coprocessor Format Words............................................................. 7-18
7.2.3.2.1 Empty/Reset Format Word........................................................... 7-18
7.2.3.2.2 Not-Ready Format Word .............................................................. 7-19
7.2.3.2.3 Invalid Format Word ..................................................................... 7-19
7.2.3.2.4 Valid Format Word ....................................................................... 7-20
7.2.3.3 Coprocessor Context Save Instruction ............................................ 7-20
7.2.3.3.1 Format .......................................................................................... 7-20
7.2.3.3.2 Protocol........................................................................................ 7-21
7.2.3.4 Coprocessor Context Restore Instruction........................................ 7-22
7.2.3.4.1 Format .......................................................................................... 7-22
7.2.3.4.2 Protocol........................................................................................ 7-23
7.3 Coprocessor Interface Register Set........................................................ 7-24