Interface Configuration Guide 7705 SAR Interfaces
Edition: 01 3HE 11011 AAAC TQZZA 747
 
Output Example
*A:ALU-1># show port 1/4/1.e1 acr detail
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Adaptive Clock Recovery (ACR) Configuration
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Clock Master PW : 1/4/1.1
Clock Sync State : normal
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CEM SAP Configuration Information
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Endpoint Type : NxDS0 Bit-rate : 16
Payload Size : 32 Jitter Buffer : 5
Use RTP Header : No Differential : No
Timestamp Freq : 0 CAS Framing : No CAS
Effective PDVT : +/-2.500 ms
Cfg Alarm : stray malformed pktloss overrun underrun
Alarm Status :
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CEM SAP Statistics
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Packets Seconds Events
Egress Stats
Forwarded : 32993106
Dropped : 0
Missing : 0
Reordered Forwarded : 0
Underrun : 8058 0
Overrun : 0 0
Misordered Dropped : 0
Malformed Dropped : 0
LBit Dropped : 0
Error : 3
Severely Error : 2
Unavailable : 0
Failure Count : 1
Jitter Buffer Depth : 0
Ingress Stats
Forwarded : 32995595
Dropped : 0
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Adaptive Clock Recovery (ACR)
- Internal Digital Phase Locked Loop (DPLL) Statistics
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frequency frequency phase phase
offset offset error error
mean stddev mean stddev
time (ppb) (ppb) (ns) (ns)
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10/08/2008 11:27:11 220 1 273 94
10/08/2008 11:26:11 217 1 240 120
10/08/2008 11:25:11 214 1 79 157
10/08/2008 11:24:11 214 1 -15 102
10/08/2008 11:23:11 214 1 82 117
10/08/2008 11:22:11 213 1 12 113
10/08/2008 11:21:11 213 1 -64 119
10/08/2008 11:20:11 213 1 -66 126