USB and PCI Express
NVIDIA Jetson Nano DG-09502-001_v2.1 | 16
Pin # Module Pin Name Tegra X1 Signal Usage/Description
Usage on NVIDIA DevKit
Carrier Board
Direction Pin Type
Code
Power-on
Reset
155 PCIE0_RX3_N PEX_RX1N
PCIe #0 Receive 3 (PCIe Ctrl #0 Lane 3)
− −
157 PCIE0_RX3_P PEX_RX1P − −
179 PCIE_WAKE* PEX_WAKE_N
PCIe Wake. 100kΩ pull-up to 3.3V on the
module.
M.2 Key E Input
Open Drain 3.3V ,
Pull-up on the
module
DD z
181 PCIE0_RST* PEX_L0_RST_N
PCIe #0 Reset (PCIe Ctrl #0). 4.7kΩ pull-up to
3.3V on the module.
Not Assigned Output
Open Drain 3.3V ,
Pull-up on the
module
DD 0
134 PCIE0_TX0_N PEX_TX4N
PCIe #0 Transmit 0 (PCIe Ctrl #0 Lane 0) M.2 Key E
Output
PCIe PHY, AC-
Coupled on carrier
board
− −
136 PCIE0_TX0_P PEX_TX4P − −
140 PCIE0_TX1_N PEX_TX3N
PCIe #0 Transmit 1PCIe Ctrl #0 Lane 1)
Not Assigned
− −
142 PCIE0_TX1_P PEX_TX3P − −
148 PCIE0_TX2_N PEX_TX2N
PCIe #0 Transmit 2 (PCIe Ctrl #0 Lane 2)
− −
150 PCIE0_TX2_P PEX_TX2P − −
154 PCIE0_TX3_N PEX_TX1N
PCIe #0 Transmit 3 (PCIe Ctrl #0 Lane 3)
− −
156 PCIE0_TX3_P PEX_TX1P − −
160 PCIE0_CLK_N PEX_CLK1N
PCIe #0 Reference Clock (PCIe Ctrl #0) M.2 Key E Output PCIe PHY
−
0
162 PCIE0_CLK_P PEX_CLK1P − 0
180 PCIE0_CLKREQ* PEX_L0_CLKREQ_N
PCIE #0 Clock Request (PCIe Ctrl #0). 47kΩ
pull-up to 3.3V on the module.
Not Assigned Bidir
Open Drain 3.3V ,
Pull-up on the
module
DD z
161 USBSS_RX_N PEX_RX6N
USB SS Receive (USB 3.0 Ctrl #0)
USB 3.0 Type A
Input
USB SS PHY, AC-
Coupled only if
direct connect to
dev ice
− −
163 USBSS_RX_P PEX_RX6P − −
166 USBSS_TX_N PEX_TX6N
USB SS Transmit (USB 3.0 Ctrl #0) Output
USB SS PHY, AC-
Coupled on carrier
board
− −
168 USBSS_TX_P PEX_TX6P
− −
Notes:
1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals.
2. The directions for PCIE_WAKE*, PCIE0_RST*, and PCIE0_CLKREQ are true when used for those functions. Otherwise as GPIOs, the
direction is bidirectional.
3. The MPIO Pad Codes are described in the
Tegra X1 SoC Technical Reference Manual
“Multi-Purpose I/O Pins and Pin Multiplexing
(PinMux)” section for details.
4. The Power-on Reset State column indicates the pin state when reset is active and when it is deactivated before any changes are made by
software. “z” is tristate, pu/pd indicates internal weak pull-up/down resistor is enabled, 1/0 indicates actively driven high/low.
Table 6-3 lists the mapping options for Jetson Nano.
Table 6-3. Jetson Nano USB 3.0 and PCIe Lane Mapping
Configurations
for Ethernet on
DevKit Carrier
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