USB and PCI Express
NVIDIA Jetson Nano DG-09502-001_v2.1 | 18
6.1.1 USB 2.0 Design Guidelines
These requirements apply to the USB 2.0 controller PHY interfaces: USB[2:0]_D_N/P.
Table 6-4. USB 2.0 Interface Signal Routing Requirements
Max frequency (high speed) Bit Rate/UI period/Frequency 480/2.083/240 Mbps/ns/MHz
Max loading High Speed / Full Speed / Low Speed 10 / 150 / 600 pF
Reference plane GND
Trace impedance Diff pair / SE 90 / 50 Ω ±15%
Via proximity (signal to reference) < 3.8 (24) mm (ps) See Note 1
Max trace length/delay Microstrip / Stripline 6 (960) In (ps)
Max intra-pair skew between
and
7.5 ps
Notes:
1. Up to four signal vias can share a single GND return via.
2. Adjustments to the USB drive strength, slew rate, termination value settings should not be necessary, but if any are made, they MUST be done as an offset
to default values instead of overwriting those values.
6.1.2 USB 3.0 Design Guidelines
The requirements following apply to the USB 3.0 port #0 PHY interface: USBSS_TX_N/P,
USBSS_RX_N/P
.
Table 6-5. USB 3.0 Interface Signal Routing Requirements
Parameter Requirement Units Notes
Specification
Data rate / UI period 5.0 / 200 Gbps / ps
Max number of loads 1 load
Termination 90 differential Ω
On-die termination at TX and RX
Insertion loss @ 2.5GHz Type-C
Type A
Resonance dip frequency
<=2
<=7
>8
dB
dB
GHz
Only PCB with add-on components (connector excluded) is
considered
TDR dip
>= 75 Ω Using TDR pulse with Tr (10%-90%) = 200ps
Near-end crosstalk (NEXT) @ DC to 5GHz
<=-45 dB For each TX-RX NEXT
IL/NEXT plot See Figure 6-2
Impedance
Reference plane GND
Trace impedance Diff pair / SE 85-90 / 45-55 Ω ±15%
Trace Spacing – for TX/RX non-interleaving
TX-RX Xtalk is very critical in PCB trace routing. The ideal solution is to route TX and RX on different layers.
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