Nvidia JETSON NANO - Figure 7-7. HDMI Connection Example; Hdmi

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NVIDIA Jetson Nano DG-09502-001_v2.1 | 37
7.3.1 HDMI
This section shows the HDMI connection requirements, signal routing requirements, and
topology.
Figure 7-7. HDMI Connection Example
Jetson
10 0k Ω
10 kΩ 10 kΩ
VDD_3V3_HDMI
1. 8kΩ 1. 8kΩ
VDD_5V0_HDMI_CON
Tegra
- HDMI
HDMI_DP_TXDN3
HDMI_DP_TXDP3
HDMI_DP_TXDN2
HDMI_DP_TXDP2
HDMI_DP_TXDN1
HDMI_DP_TXDP1
HDMI_DP_TXDN0
HDMI_DP_TXDP0
DP_AUX_CH1_P
DP_AUX_CH1_N
HDMI_INT_DP_HPD
DP
HDMI
HDMI_CEC
10 kΩ
10 0k Ω
96
100
98
94
65
63
71
69
77
83
81
75
DP1_HPD
DP1_AUX_P
DP1_AUX_N
HDMI_CEC
DP1_TXD3_N
DP1_TXD3_P
DP1_TXD2_N
DP1_TXD2_P
DP1_TXD1_N
DP1_TXD1_P
DP1_TXD0_N
DP1_TXD0_P
MOD_SLE EP*
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
499Ω,1%
VDD_1 V8
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
See
Note 4
T PD4E 02B 04 DQO R
VDD_5 V_IN
HDMI
Type A
H P_ DE T
+5V
D D C/ CE C_ GN D
SDA
SCL
RESE RVED
CEC
CK–
CK_SHIELD
CK+
D0–
D0_ SHIELD
D0+
D1–
D1_ SHIELD
D1+
D2–
D2_ SHIELD
D2+
1
3
5
11
7
9
13
15
17
19
2
10
12
6
8
14
16
18
4
VDD_3 V3_SY S VDD_3V3_HDMI
10 kΩ
10 0k Ω
0. 1uF
Load Switch
EN
IN OUT
Lev el Shifte r
1.8V 5V
CEC Lev el
Shifter Circuit
(se e not e)
Lev el Shifte r
3.3V 5V
Load Switch
EN
IN OUT
FET
DG
S
Notes:
1. Level shifters required on DDC/HPD. Tegra pads are not 5V tolerant and cannot directly meet HDMI VIL/VIH
requirements. HPD level shifter can be non-inverting or inverting. HPD level shifter on the Jetson Nano
Developer Kit is inverting.
2. If EMI/ESD devices are necessary, they must be tuned to minimize the impact to signal quality, which must
meet the timing and electrical requirements of the HDMI specification for the modes to be supported. See
requirements and recommendations in the related sections of Table 7-10.
3. The DP1_TXx pads are native DP pads and require series AC capacitors (ACCAP) and pull-downs (RPD) to be
HDMI compliant. The 499Ω, 1% pull-downs must be disabled when Jetson Nano is off or in sleep mode to meet
the HDMI VOFF requirement. The enable to the FET, enables the pull-downs when the HDMI interface is to be
used. Chokes between pull-downs and FET are optional improvements for HDMI 2.0 operation.
4. Series resistors RS are required. See the RS section of Table 7-10 for details.
5. See reference design for CEC level shifting/blocking circuit.