Nvidia JETSON NANO - Figure 11-4. SPI Topologies; SPI Design Guidelines; Table 11-5. SPI Interface Signal Routing Requirements

Miscellaneous Interfaces
NVIDIA Jetson Nano DG-09502-001_v2.1 | 61
11.2.1 SPI Design Guidelines
Figure 11-4 shows the SPI topologies and Table gives the SPI interface signal routing
requirements.
Figure 11-4. SPI Topologies
Jetson
SPI
Device
#1
Main trunk
SPI
Device
#2
SPI
Device
#1
Main trunk
SPI
Device
#2
Branch-A
Branch-B
Branch-A
Branch-B
2x-Load Star Topology 2x-Load Daisy Topology
SPI
Device
Main trunk
Tegra
Jetson
Tegra
Jetson
Tegra
Point-Point Topology
Table 11-5. SPI Interface Signal Routing Requirements
Parameter Requirement Units Notes
Max frequency 65 MHz
Configuration / device organization 4 load
Max loading (total of all loads) 15 pF
Reference plane GND
Breakout region impedance Minimum width and
spacing
Max PCB breakout delay 75 ps
Trace impedance 50 – 60 Ω ±15%
Via proximity (signal to reference) < 3.8 (24) mm (ps) See note
Trace spacing Microstrip / Stripline 4x / 3x dielectric
Max trace length/delay (PCB main trunk) Point-point
For
MOSI, MISO, SCK
and
CS
2x-load star/daisy
195 (1228)
120 (756)
mm (ps)
Max trace length/delay (Branch-A) 2x-load star/daisy
for
MOSI, MISO, SCK
and
CS
75 (472) mm (ps)
Max trace length/delay skew from
MOSI, MISO
and
CS
to
SCK
16 (100) mm (ps) At any point
Note: Up to four signal vias can share a single GND return via.