Display
NVIDIA Jetson Nano DG-09502-001_v2.1 | 31
7.2 eDP and DP
Table 7-5 details the MIPI DSI and CSI connection pin descriptions for the eDP and DP
displays.
Table 7-5. Jetson Nano eDP and DP Pin Description
Pin # Module Pin Name Tegra X1 Signal Usage/Description
Usage on NVIDIA DevKit
Carrier Board
Direction Pin Type
Code
Power-on
Reset
90 DP0_AUX_N DP_AUX_CH0_N
Display Port 0 auxiliary channel
DP connector
Bidir
AC-Coupled on
Carrier Board
(eDP/DP)
DP_AUX z
92 DP0_AUX_P DP_AUX_CH0_P
DP_AUX z
39 DP0_TXD0_N EDP_TXDN0
Display port 0 data lane 0
Output
AC-Coupled on
carrier board
− z
41 DP0_TXD0_P EDP_TXDP0 − z
45 DP0_TXD1_N EDP_TXDN1
Display port 0 data lane 1
− z
47 DP0_TXD1_P EDP_TXDP1 − z
51 DP0_TXD2_N EDP_TXDN2
Display port 0 data lane 2
− z
53 DP0_TXD2_P EDP_TXDP2 − z
57 DP0_TXD3_N EDP_TXDN3
Display port 0 data lane 3
− z
59 DP0_TXD3_P EDP_TXDP3 − z
88 DP0_HPD DP_HPD0 Display port 0 hot-plug detect Input CMOS – 1.8V ST pd
Notes:
1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals.
2. The direction for DP0_HPD is true when used for this function. Otherwise as a GPIO, the direction is bidirectional
3. The MPIO Pad Codes are described in the
Tegra X1 SoC Technical Reference Manual
“Multi-Purpose I/O Pins and Pin Multiplexing
(PinMux)” section for details.
4. The Power-on Reset State column indicates the pin state when reset is active and when it is deactivated before any changes are made by
software. “z” is tristate, pu/pd indicates internal weak pull-up/down resistor is enabled, 1/0 indicates actively driven high/low.
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