Nvidia JETSON NANO - Figure 7-8. HDMI Clk and Data Topology; Table 7-10. HDMI Interface Signal Routing Requirements

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NVIDIA Jetson Nano DG-09502-001_v2.1 | 38
Figure 7-8. HDMI Clk and Data Topology
100Ω*
100Ω*
100Ω*
100Ω*
100Ω*
100Ω*
Jetson
HDMI
Conn
AC
C AP
Se g D Seg F
MOD_SL EE P*
49 9Ω,
1%
PCB Vias
PCB Vias
0. 1uF
0. 1uF
R
PD
Com mon Mo de
Cho kes & ES D
Se e No te 1
49 9Ω,
1%
Se g B Se g E
Se g C
Tegra
95-100Ω 100Ω*
95-100Ω 100Ω*
Main Route –
Se g A
* Note 3 * Note 3* Note 3 * Note 3
R
S
(See Not e 4 )
Choke or Trace
Se e No te 2
Notes:
1.RPD pad must be on the main trace. RPD and ACCAP must be on same layer.
2.Chokes (600Ω @ 100 MHz) or narrow traces (1uH@DC-100 MHz) between pull-downs and FET are
chokes between pull-downs and FET are optional improvements for HDMI 2.0 operation.
3.The trace after the main route via should be routed on the top or bottom layer of the PCB, and
either with 100 ohm differential impedance, or as uncoupled 50 ohm SE traces.
4.RS series resistor is required. See the RS section of Table 7-10 for details.
Table 7-10. HDMI Interface Signal Routing Requirements
Parameter Requirement Units Notes
Specification
Max frequency / UI 5.94 / 168 Gbps / ps Per lane – not total link bandwidth
Topology Point to point Unidirectional, differential
Termination At receiver
On-board
100
500
Ω Differential To 3.3V at receiver
To GND near connector
Electrical Specification
IL
resonance dip frequency
<= 1.7
<= 2
<= 3
< 6
> 12
dB @ 1GHz
dB @ 1.5GHz
dB @ 3GHz
dB @ 6GHz
GHz
TDR dip >= 85 Ω @ Tr=200ps 10%-90%. If TDR dip is 75~85ohm that dip width
should < 250ps
FEXT (PSFEXT) <= -50
<= -40
<= -40
dB at DC
dB at 3GHz
dB at 6GHz
PSNEXT is derived from an algebraic summation of
the individual NEXT effects on each pair by the
other pairs
IL/FEXT plot: See Figure 7-9 TDR plot: See Figure 7-10
Impedance
Trace impedance Diff pair 100 Ω ±10%. Target is 100Ω. 95Ω for the breakout and
main route is an implementation option.