Nvidia JETSON NANO Product Design Guide

NVIDIA Jetson Nano DG-09502-001_v2.1 | 46
Chapter 8. MIPI CSI Video Input
Jetson Nano brings twelve MIPI CSI lanes to the connector. Three quad-lane camera streams
or two quad-lane plus two dual-lane camera streams or one quad-lane plus three dual-lane
camera streams are supported. Each data lane has a peak bandwidth of up to 1.5 Gbps.
Note: In Table 8-1 and Table 8-2 the Direction column, the Output is from Jetson Nano and the
Input is to Jetson Nano. Bidir is for bidirectional signals.
Table 8-1. Jetson Nano CSI Pin Description
Pin # Module Pin Name Tegra X1 Signal Usage/Description
Usage on NVIDIA DevKit
Carrier Board
Direction Pin Type
MPIO Pad
Code
Power-on
Reset
10 CSI0_CLK_N CSI_A_CLK_N
Camera, CSI 0 Clock
Camera Connector #1
Input MIPI D-PHY
−
z
12 CSI0_CLK_P CSI_A_CLK_P
−
z
4 CSI0_D0_N CSI_A_D0_N
Camera, CSI 0 Data 0
− z
6 CSI0_D0_P CSI_A_D0_P − z
16 CSI0_D1_N CSI_A_D1_N
Camera, CSI 0 Data 1
−
z
18 CSI0_D1_P CSI_A_D1_P
−
z
3 CSI1_D0_N CSI_B_D0_N
Camera, CSI 1 Data 0
Not Assigned
− z
5 CSI1_D0_P CSI_B_D0_P − z
15 CSI1_D1_N CSI_B_D1_N
Camera, CSI 1 Data 1
−
z
17 CSI1_D1_P CSI_B_D1_P
−
z
28 CSI2_CLK_N CSI_E_CLK_N
Camera, CSI 2 Clock
Camera Connector #2
− z
30 CSI2_CLK_P CSI_E_CLK_P − z
22 CSI2_D0_N CSI_E_D0_N
Camera, CSI 2 Data 0
−
z
24 CSI2_D0_P CSI_E_D0_P
−
z
34 CSI2_D1_N CSI_E_D1_N
Camera, CSI 2 Data 1
− z
36 CSI2_D1_P CSI_E_D1_P − z
27 CSI3_CLK_N CSI_F_CLK_N
Camera, CSI 3 Clock
Not Assigned
−
z
29 CSI3_CLK_P CSI_F_CLK_P
−
z
21 CSI3_D0_N CSI_F_D0_N
Camera, CSI 3 Data 0
− z
23 CSI3_D0_P CSI_F_D0_P − z
33 CSI3_D1_N CSI_F_D1_N
Camera, CSI 3 Data 1
−
z
35 CSI3_D1_P CSI_F_D1_P
−
z
52 CSI4_CLK_N CSI_C_CLK_N
Camera, CSI 4 Clock
− z
54 CSI4_CLK_P CSI_C_CLK_P − z

Nvidia JETSON NANO Specifications

General

Brand	Nvidia
Model	JETSON NANO
Category	Microcontrollers
Language	English