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NVIDIA Jetson Nano DG-09502-001_v2.1 | 33
7.2.1 eDP Routing Guidelines
Figure 7-3 shows the eDP topology, and Table gives the eDP and DP signal routing
requirements.
Figure 7-3. eDP Differential Main Link Topology
Jetson
eDP
Conn
Tegra
Pkg
DP
Dri ver
P
N
Com mon Mo de
Cho kes & ES D
Table 7-6. eDP and DP Main Link Signal Routing Requirements including
DP_AUX
Parameter Requirement Units Notes
Specification
Max data rate / Min UI R
1.62 / 617
2.7 / 370
5.4 / 185
Gbps / ps Per data lane
Number of loads / topology 1 load Point-Point, differential, unidirectional
Termination 100 Ω On die at TX/RX
Electrical Spec
IL
0.7
1.2
2.4
dB @ 0.81GHz
dB @ 1.35GHz
dB @ 2.7GHz
Resonance dip frequency >8 GHz
TDR dip >85 Ω @ Tr-200ps (10%-90%)
FEXT <= -40dB @ DC
<= -30dB @ 2.7GHz
See Figure 7-4
Impedance
Trace impedance Diff pair 90-100
85
Ω (±15%) 90Ω–100Ω is the spec. target. 85Ω is an implementation
option (Zdiff does not account for trace coupling)
85Ω is preferable as it can provide better trace loss
characteristic performance. See Note 1.
Reference plane
Trace Length, Spacing and Skew
Trace loss characteristic: < 0.81 dB/in
@ 2.7GHz. The following max length is derived based on
this characteristic. See Note 2.
Max PCB via dist. from connector
No requirement
7.63 (0.3)
mm (in)
Max trace length/delay from Jetson Nano TX to
connector
(Stripline / Microstrip)
215 (1138)/215 (975)
mm (ps)
175ps/inch assumption for stripline, 150ps/inch for
microstrip.
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