Nvidia JETSON NANO - Page 42

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NVIDIA Jetson Nano DG-09502-001_v2.1 | 34
Parameter Requirement Units Notes
HBR2 (Stripline)
HBR2
(Microstrip, 5x / 7x)
102 (700)
89 (525) / 102 (600)
Trace spacing (pair-pair) Stripline
Microstrip (
HBR/RBR
)
Microstrip (
HBR2
)
3x
4x
5x to 7x
dielectric
Trace spacing Stripline/Microstrip
(Main link to AUX)
3x / 5x dielectric
Max intra-pair (within pair) skew 0.15 (1) mm (ps) See Note 2
Maxinter-pair (pair-pair ) skew 150 ps See Note 3
Via
Max
GND
transition via distance < 1x diff pair pitch For signals switching reference layers, add symmetrical
GND
stitching via near signal vias.
Via Structure
Impedance dip
Recommended via dimension Drill/Pad
for impedance control Antipad
Via pitch
≥97
≥92
200/400
>840
≥880
Ω @ 200ps
Ω @ 35ps
um
um
um
The via dimension is required for HDMI-DP co-la yout.
Topology Y-pattern is recommended
keep symmetry
Y-pattern helps with Xtalk suppression. It can also
reduce the limit of pair-pair distance. Need review
(NEXT/FEXT check) if via placement is not Y-pattern. See
Figure 7-5
For in-line via, the distance from a via of one
lane to the adjacent via from another lane >=
1.2 mm center-center.
See Figure 7-6
GND
via
Place
GND
via as symmetrically as possible
to data pair vias. Up to four signal vias (2 diff
pairs) can share a single
GND
return via
GND
via is used to maintain a return path, while its Xtalk
suppression is limited.
Max # of vias PTH vias
Micro vias
2 if all vias are PTH via
Not limited if total channel loss meets IL spec
Max via stub length 0.4 mm
AC Cap
Value 0.1 uF Discrete 0402
Max distance from AC cap
RBR/HBR
to connector
HBR2
No requirement
0.5 in
Voiding
RBR/HBR
HBR2
No requirement
Voiding required
HBR2
: Voiding the plane directly under the pad 3-4 mil s
larger than the pad size is recommended.
Connector
Voiding
RBR/HBR
HBR2
No requirement
Voiding required
HBR2:
Standard DP connector: Voiding requirement is
stack-up dependent. For typical stack-ups, voiding on the
layer under the connector pad is required to be 5.7 mil
larger than the connector pad.
General: See Chapter 15 for guidelines related to Serpentine routing, routing over voids and noise coupling
Notes:
1. For eDP/DP, the spec puts a higher priority on the trace loss characteristic than on the impedance. However, before selecting 85Ω for impedance, it is important
to make sure the selected stack-up, material and trace dimension can achieve the needed low loss characteristic.
2. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace lengths will need to be
reduced.
3. Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before vias or any discontinuity to minimize common
mode conversion.
4. The average of the differential signals is used for length matching.