Nvidia JETSON NANO Product Design Guide

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NVIDIA Jetson Nano DG-09502-001_v2.1 | 45
7.3.2.1 DP Interface Signal Routing Requirements
See eDP and DP signal routing requirements.
Table 7-12. DP Signal Connections
Module Pin Name Type Termination (see note on ESD) Description
DP1_TXD3_N/P
DP1_TXD[2:0]_N/P
O Series 0.1uF capacitors → ESD on all.
DP Differential Lanes:
Connect to
D[3:0] –/+.
See DP/HDMI pin mapping table for correct
connections of data pins.
DP1_HPD I From Module pin: 10kΩ pull-up to 1.8V → level
shifter and 100kΩ pulldown on connector side of
shifter → ESD to
GND
.
DP Interrupt (Hot Plug Detect): Connect to
HPD
pin on DP connector w/termination
described.
DP1_AUX_N/P I/OD From module pins: series 0.1uF caps → then
100KΩ PD on
AUX_P
and 100KΩ PU to 3.3V on
AUX_N
→ ESD.
DP: Auxiliary Channels
: Connect to
AUX_CH–
/+
on DP connector
DP 3.3V Supply
P Adequate decoupling (0.1uF and 10uF
recommended) on supply near connector.
DP supply to connector: Connect 3.3V supply
pin on DP connector to VDD_3V3_SYS.
Note: Any ESD and/or EMI solutions must support targeted modes (frequencies).

Nvidia JETSON NANO Specifications

General

Brand	Nvidia
Model	JETSON NANO
Category	Microcontrollers
Language	English